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Rinse/Dry Steps Get New Look at SPCC

The Sematech Surface Preparation and Cleaning Conference (SPCC) opened with several presentations on how to reduce water, chemical and energy usage during cleaning steps. A study conducted at the University of Arizona, with participation from Samsung Electronics Co., employed on-wafer sensors to monitor residual impurity concentrations during hot rinse and spin dry steps.

David Lammers, News Editor -- Semiconductor International, 3/25/2009

Rinsing and drying techniques are getting more attention as semiconductor companies seek to become more environmentally benign, speakers said at the Sematech Surface Preparation and Cleaning Conference (SPCC, Austin, Texas). Challenges — ranging from cleaning high-aspect-ratio devices to rinsing and drying layers with hydrophobic low-k dielectrics — are driving companies to new approaches, often using single-wafer cleaning tools with shorter process times.

Jeongnam Han, Samsung Electronics
Jeongnam Han, Samsung Electronics

Jeongnam Han, a member of the process R&D staff, said Samsung Electronics Co. (Seoul, South Korea) is using an Electro-Chemical Residue Sensor (ECRS) developed by Environmental Metrology Corp. (EMC, Tucson, Ariz.) a spinoff from the University of Arizona.

Dhane Kedar, University of Arizona

Dhane Kedar, University of Arizona

Founded in 2003 by Arizona professor Farhang Shadman, Bert Vermeire and others, the company has signed up several chip companies to employ the ECRS for in situ monitoring of impurities on wafers. Multiple ECRSs, built from silicon and poly, are used to monitor the residual impurity concentrations on a wafer during rinsing and spin drying steps, said Kedar Dhane, a graduate research assistant at the University of Arizona. Several companies, including Samsung and Freescale Semiconductor Inc.’s Tempe, Ariz. facility, are working with EMC, Dhane said.

Han said one objective at Samsung is to reduce the amount of de-ionized water and chemicals used in cleaning steps. Using hot rinses at 70°C, for example, may help to minimize rinse times and clean heterogeneous structures, which have both hydrophilic and hydrophobic structures.

While Samsung now uses single-wafer rinse/dry tools extensively in its memory operations, the company is still investigating whether to employ hot rinse cycles. One challenge is that hot rinses create steam that can leave water marks on wafers. Another hurdle is the extra cost involved with putting in hot water lines to rinsing tools, he said.

Han spent several months in Tucson participating in a study of how staged hot and cold rinses can help clean the high-aspect structures now seen in memory chips. The effort involves combining ECRS metrology with process modeling to identify bottlenecks in cleaning, rinsing and drying steps, Dhane said.

Hot water at a moderate flow rate of 5 GPH may provide the best results, according to a University of Arizona study that employed on-chip sensors.
Hot water at a moderate flow rate of 5 GPH may provide the best results, according to a University of Arizona study that employed on-chip sensors.

Low gamma solvent

During the evening poster session at SPCC, Yannick Le Tiec described his team’s work at the Leti research laboratory (Grenoble, France) to develop new drying techniques. Leti’s goal is to control the water amount on the oxide or silicon surface prior to the wafer-bonding step, which is key to silicon-on-oxide (SOI) wafer manufacturing. The Smart Cut SOI process was first developed by researchers at Leti more than 15 years ago. “For floating body cell (FBC) memory applications, the targeted buried oxide layer is about 10 nm,” Le Tiec said. Working with researchers from FSI International Corp.’s Bernin, France center, the Leti team has come up with a low surface tension solvent, which the group identifies as Low Gamma Solvent (LGS). The goal is to replace standard isopropyl alcohol (IPA) with LGS, which has a surface tension much lower than IPA. The LGS would enable drying with minimal amounts of water left on the surface prior to bonding, which would prevent water from reacting with silicon to form undesired hydrogen bubbles within the interface of the buried oxide and the bottom silicon substrate.

The technique may be suitable for optimized front-end-of-line cleaning and drying steps. “Everyone thinks drying is so simple, but it is not,” LeTiec said.

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