3-D Goes Beyond Simplifying Interconnect
Laura Peters, Lead Technical Editor -- Semiconductor International, 10/18/2007
“Ten years from now we won’t be asking ‘Why 3-D?,’ we’ll be asking ‘Why 2-D?’” said Jochen Reisinger of Infineon Technologies AG (Munich, Germany). Reisinger was one of four panelists who discussed 3-D integration for system design at IMEC’s annual review meeting, held Oct. 15-16.
Eric Beyne, scientific director of InterConnect, Packaging and Systems Integration at IMEC (Leuven, Belgium), said that 3-D is not just about taking chips as they are and stacking them. He said that by focusing on system design requirements, the true benefits of 3-D can be realized. Fred Roozeboom, Research Fellow at NXP Semiconductors Research (Eindhoven, Netherlands), elaborated on this point, saying, “For now, we’re talking about just the interconnect between two chips, but with 3-D, the chips can interact with each other, which is absolutely new.”
Of course, the key driver for 3-D integration is cost savings. Cost benefits, particularly around the 45 nm node, become more apparent. Roozeboom said that at a flash capacity of >64 Gb, they expect a large cost difference between 2-D and 3-D approaches. IMEC’s Diederik Verkest offered that a 45 nm 3-D approach could prove less expensive than bringing a 32 nm planar device to market. “Only in very few cases will costs not define the entry date for new technologies,” Reisinger said.
Roozeboom estimated that ~90% of the 3-D devices produced today are stacked packages, most commonly stacked memory devices, but also sensors including CMOS imaging sensors. But as Beyne explained, 3-D can be introduced at different levels to achieve 3-D system-in-a-package (SiP; stacked packages, typically wire bonded), 3-D wafer-level packaging (WLP; bump and redistribution layer) or 3-D IC (interconnected at the global or intermediate levels of the chip). He added that the most difficult aspect of chip-to-chip 3-D processing is achieving the overlay accuracy required for micron-sized vias.
Reisinger pointed out additional difficulties with implementing 3-D. He said that testing and quality assurance is challenging. Also, ultimately, the design community needs to produce hierarchical design flows with standardized data interfaces. Roozeboom said that like silicon devices, the industry needed classification and roadmapping for 3-D. He predicted that the first companies to implement 3-D will be the device manufacturers themselves, which will later be followed by foundries and subcontractors. “Over the next five years, it will be the silicon guys,” he said. Infineon proposed a passive carrier with through-silicon holes to act as chip-to-board interfaces (an interposer). It’s made out of silicon to match the thermal expansion coefficient of the chip and carrier (Figure). Such a solution is designed to meet the geometrical, thermal, mechanical and electrical challenges of matching ICs with dense interconnects with a PCB with standard or advanced area-array pitches (Table).
| This passive silicon carrier contains a regular grid of through-silicon vias (TSVs). It is designed to serve as a cost-optimized interposer for standard circuit ICs, with matching coefficient of thermal expansion to the chip and carrier. (Source: Infineon) |
Back in July, IMEC announced that it was extending its 3-D system integration program, putting emphasis on the link between technology development and design methodologies. The research center proposes that a universal communication fabric must be developed (including clock and power distribution) to enable interconnection of components in separate layers, possibly fabricated in different technologies (true heterogeneous integration).
At the annual review meeting this week, IMEC announced a partnership with the Georgia Institute of Technology (Atlanta), a program focused on next-generation flip-chip and substrate technology designed to address the IC/package interconnect gap. The interconnect gap refers to the difference between the rapid progress in chip-level interconnect scaling that is expected between now and 2015 (from 60-20 µm peripheral pitches), relative to the density of interconnects on PCBs (800-500 µm solder ball pitch). With ball grid array (BGA) and micro-BGA approaches, package reliability is dominated by underfill reliability. Smaller diameter bumps put more strain on thinner layers and higher stresses on smaller areas.
The program targets novel packaging approaches to reduce the mechanical stress on the IC after packaging and assembly. These low-stress packaging techniques become indispensable when using copper/low-k on-chip interconnections, because low-k materials typically have very weak mechanical properties.
The aim of the program is to explore organic package interposer substrates that minimize stress at the die and package level and enhances wiring density, the fine I/O pitch routing capability and the high-frequency signal performance of substrates; a new generation of fine-pitch flip-chip under-bump metallization (UBM) and barrier metallization that meet the electromigration and thermomechanical reliability targets of flip-chip scaling; novel solder and non-solder interconnect approaches including advanced underfill materials and processes to meet future requirements; and thermomechanical modeling, design and verification for improved reliability.
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