Flow-Over-Wire Materials Enable Die Stacking

Recent advances in flow-over-wire (FOW) technologies, including FOW pastes and films, are enabling packaging engineers to design thinner packages, reduce manufacturing process steps and drive down overall package costs.

Michael Todd, Henkel Corp., Irvine, Calif. -- Semiconductor International, 12/1/2008

1. Stacked-die chip-scale packages combine two or more ICs into a single package by stacking the die, interconnecting them with wire bonding and molding the assembly into a standard package.

Traditional single die IC packaging designs are being replaced by more complex, multi-die packaging configurations for today's in-demand applications. With the trend toward products offering more functionality and higher performance at a lower cost, package designers are using stacked-die chip-scale packages (SCSPs) and the like to provide higher performance while consuming the same footprint as conventional single-die packages. SCSPs combine two or more ICs, such as an ASIC and memory (SRAM and DDR), into one package by stacking the die, interconnecting them with wire bonding and molding everything into one standard package (Fig. 1). These packages provide a smaller footprint and lower profile compared with nonstacked packages. They also have lower packaging costs vs. individually packaged die or other 3-D packages.

Extensive work has been published on stacked-die package designs, including die layout and wire bond optimization schemes, thin die handling processes and electrical/RF performance optimization.^1-3 The packaging materials used in stacked-die packages, however, are often not well understood. Each material used in these complex IC packages interacts with the others to generate interfaces and stresses that contribute to overall package performance. Furthermore, the material systems are important factors in the cost and manufacturing process complexity of packaged devices. To minimize costs associated with redesign or rework, it is critical to select the right materials system for a package in the design phase.

This article* will discuss the die-attach technologies for stacked-die packages, generally known as flow-over-wire (FOW), in which a paste is applied between each die prior to or during die placement. The FOW die-attach material provides a low-stress bond between each die and serves to hold the die securely in place during wire bonding. It also provides a controlled thickness gap between each die within the stack to prevent crushing of the wire bonds between each die. FOW technology was first demonstrated using spacer-filled die-attach pastes almost 10 years ago. More recently, film versions of the FOW have emerged as a means to facilitate the die bonding manufacturing process.

Materials for stacked packages

Early in the development of the first S CSPs, engineers discovered that traditional die-attach pastes were not able to meet the requirements for this new type of IC package. In particular, the high modulus of traditional epoxy die-attach materials as well as the abrasive fillers used in these materials prevented their use between stacked die. The high modulus die-attach materials created large stresses within the stacked die packages, resulting in die cracking and delamination. The typical fillers used in nonconductive die attaches were hard and abrasive and scratched the surface passivation of the active side of the die during the die placement process, resulting in electrical failures. Therefore, a lower-stress, nonabrasive family of die-attach materials was designed for use between stacked die, resulting in lower die-to-die stress and negligible passivation damage from die-attach abrasion.

These materials were successfully used in pyramid die stack IC configurations. However, for the same-size die stack configurations, additional bond-line control was needed to prevent damaging wire bonds of the lower die when the upper die was placed on top. For this reason, spacer-filled FOW paste materials were developed.

Early versions of these types of die-attach adhesives contained glass spheres as spacers to provide the necessary gap and die tilt control. The rigid glass spacers, however, are not compressible and introduce tiny stress points that cause die-passivation damage. Instead, the latest generation of spacer technology involves the use of polymer organic spheres. These polymer spheres serve the same purpose as their rigid counterparts, but are pliable, predictably compressible and do not cause die passivation damage.

Compared to a traditionally packaged same-size die stack using a dummy die that is placed between subsequent die stacks to maintain the ~4 mil bond line thickness, the spacer paste offers advantages in manufacturing process efficiency. The dummy die configuration requires additional process steps, including die-attach paste dispensing, die mounting and additional cure stages — all of which increase costs and decrease throughput. By using a spacer-filled paste, additional steps are eliminated and overall package height is reduced. Furthermore, modeling analysis has shown that using the same-size spacers instead of a dummy die reduces the maximum stress in the die-attach material.

DA films for thin die handling

Most stacked-die packages require wafer thinning. Thin wafers left unsupported will bow and curl under the stress of the numerous thin-film layers of the circuit and the thick passivation layer. Inline wafer thinning supports wafers on tape for better process control and minimum breakage from handling. It includes a two-step backgrind process, a rough and then fine grind, followed by a mechanical polishing that removes about 2 μm of damaged silicon and the associated stress.

The same inline system can attach a thin 20 μm die-attach film from a roll to the back of the wafer integrated on the saw tape. This technology, known as "dicing die-attach film," or DDF, enables handling of thinned wafers down to 50 μm in thickness or less. DDF replaces traditional die-attach paste in stacked packages for its good control of paste bleed, creeping effect to die edge and also consistent bond line thickness control (BLT) at desired thickness. DDF materials cannot be used over wire bonds, however, and thus are limited to only pyramid-stack or stair-step stack die configurations.

Recently, FOW film materials were introduced to allow same-size die stacking with a laminated die-attach film. The FOW film is combined with the dicing tape, similar to the DDF. When FOW film is used, a wafer is laminated on the FOW film, then diced, UV-cured (if the dicing tape is a UV tape), and die-picked and attached. During die picking, easy release and clean separation between the die bonding film and dicing film is critical. Further, die placement speed and pressure will determine the FOW total cost of use. The FOW is designed to flow over the wire bonds of the die below the one being placed. This material eliminates the need for spacer silicon die or the need to stagger sequential die.

There are many material characteristics of the FOW film that may affect the package performance and/or processing requirements. Most of the characteristics are similar to DDF and/or FOW paste, with a few notable exceptions. First, the FOW film encapsulates the wire bonds of the stacked die package, whereas the typical DDF does not. Therefore, thermal-mechanical properties as well as ionic cleanliness of the die-attach film affects the performance of the thin stacked die. If the FOW film is not ionically stable, biased HAST or humidity exposure will result in corrosion issues. Next, the viscoelastic characteristics of the film allow the film to be placed over the wire bonds without wire bond deformation or knit-line formation.

2. The FOW film must flow around the wire bonds without causing mechanical distortion.

Figure 2 shows the encapsulated wire bond wires of a stacked package built with an FOW film. Similar to DDF, the FOW films should process through wire bonding without cure to minimize process steps.
FOW process considerations

The FOW paste and film materials offer alternatives to the traditional dummy-die stack configuration used for the same-size die stack packages. As previously described, the FOW paste and film technologies eliminate the need for dummy die in stacked packages and reduce the overall complexity of the stacked die manufacturing process (Fig. 3).

3. FOW paste eliminates dummy die. The FOW film eliminates die-attach paste dispense. Pressure-sensitive FOW film eliminates the die-attach cure.

The FOW paste technology eliminates the process steps associated with placing the dummy die. The FOW film further eliminates the need for the die-attach dispense and cure process steps. The FOW technologies use existing die handling and placement equipment and require no capital infrastructure replacement to convert from traditional dummy-die stack design to FOW stack designs.

FOW technologies provide superior bond line and die tilt control over conventional die-attach processes. The narrow tolerance of the spacers used in FOW paste and the narrow tolerance of the film thickness produced in FOW films ensure accurate, reproducible bond line and tilt control.

JEDEC performance

To evaluate JEDEC performance of FOW film materials, two different two-die CSP builds were evaluated using two different FOW film technologies: one requiring oven cure, and one with a pressure-sensitive release mechanism that required no cure step.

In both cases, the FOW film performed well on a two-die CSP build. In Case 1, with oven-cure film, the material was nearly void- free with low placement force observed. In addition, there was no creep, no wire damage and excellent BLT control. In this case, a die-attach cure of 175°C for 1 hour was required. This package passed JEDEC Level II, 260°C requirements and exhibited no weld line or voids underneath the wire bonds after die placement. For this analysis, an 80-μm-thick film was used along with a 70 μm wire loop height. The process developed can be used for a variety of FOW film thicknesses and wire bond loop heights, as the FOW film is available from 50 to 80 μm, depending on the requirement for the gold wire loop height. The recommended film-to-loop height differential is 10 μm (film should be 10 μm thicker than loop height).

In this experiment, a 75-μm-thick die was used with an 80-μm-thick FOW film. A 250 × 300 μm die was used for the stack with 1 mil gold wire bonds and 70 μm wire loop height. The CSP outline size was 12 × 12 mm. Results showed some weld lines below the wire bond loops after die placement (Fig. 4). However, acoustic microscopy indicated that these weld lines were removed during the overmolding process. The stacked CSP in Case 2 passed JEDEC Level II, 260°C moisture exposure testing as well as JEDEC thermal cycle condition B testing for 2000 cycles and HAST 168 hours' exposure testing.

4. Weld lines were observed below the wire bond loops after die placement, but they were removed during the overmolding process.

Conclusions

To stay cost-competitive and production-efficient, firms building today's complex packages must do so with minimal impact on throughput. Maintaining throughput has become increasingly challenging as package designers — in response to consumer demands for smaller, higher-functioning products — must incorporate ultrathin die into stacked-die CSPs. Results from studies suggest that new FOW technologies are the most effective way to achieve a robust, high-throughput and cost-competitive process. With these next-generation materials, thinner packages with fewer process steps are achievable, which significantly reduces capital infrastructure investment and overall manufacturing cost.

*This article was originally published in the International Microsystems, Packaging, Assembly and Circuits Technology (IMPACT) conference proceedings, October 2007.

Reference

1. M. Dreiza et al., "Stacked Die Package Design Guidelines," Proceedings of IMAPS Conference, 2004.

2. M. Karnezos et al., "Stacked Die Packaging: Technology Toolbox, Step 8," Advanced Packaging, 2004.

3. D.J. Matthews et al., "RF System in Package: Considerations, Technologies and Solutions," Chip Scale Review, July 2003.