Strained Silicon: Essential for 45 nm

Silicon stressor techniques can be combined to provide cost-effective, low-risk ways of delivering next-node mobility improvements and drive currents.

Laura Peters, Senior Editor -- Semiconductor International, 3/1/2007

Classical scaling is quickly running up against a “red brick wall” as transistor dimensions reach 45 nm. With increasing circuit density, mobility enhancements become key to maintaining transistor performance as supply voltages are scaled to manage active power dissipation at the chip level. “The increasing constraints of power, performance, cost, variability and density will bind process technology ever more intimately to circuits and systems on the chip as we continue scaling,” said Aaron Thean, manager of the Novel Device Group at Freescale Semiconductor (Austin, Texas).

As a result, effective scaling has taken over, and with it, the technology of strain engineering is being widely used to speed carrier mobility (holes in pFETs and electrons in nFETs) in transistor channels, enabling much higher drive currents (I_dsat), even with modest or no decrease in gate oxide thickness. “People are still doing device shrinks, but materials engineering is playing a bigger part. Strained films are allowing the industry to stay on the performance curve, with limited changes to the transistor geometry,” said Tom St. Dennis, senior vice president and general manager at Applied Materials (Santa Clara, Calif.). In fact, even with no change in gate length, strained silicon methods, along with the simultaneous optimization of other transistor processes, can deliver next-node performance. There are essentially two types: process-induced strain, which creates strain in one direction (uniaxial); and intrinsic strain, where the substrate is inherently stressed as in strained silicon on insulator (sSOI) wafers, called biaxial strain. And, since electrons move faster in a (100) silicon substrate and holes move faster in a (110) substrate, hybrid-orientation schemes have been devised to take full advantage of geometrical preferences.

1. The top of this 300 mm epitaxial chamber shows the heating array. Across-wafer uniformity is critical to creating production-worthy SiGe S/D layers in pMOS devices. (Source: Applied Materials)

One of the wonderful things about stressor techniques is that, for the most part, they have proven to be additive. Semiconductor manufacturers have been able to combine the techniques, such as compressive stress liners and SiGe source/drain (S/D) engineering (Fig. 1), to achieve the amount of mobility enhancement needed in each transistor and raise the drive current of the device. In addition, the benefits of strain are not limited to logic transistors: For NAND flash memories, the charge retention is improved and tunneling leakage current can be reduced.¹ In DRAM, refresh times can be improved.
Stress liners and memorization

Strained silicon engineering was first used at the 90 nm node. The most straightforward and cost-effective techniques have been the process-induced straining methods, such as compressive nitride and tensile nitride layers, deposited over the gates of pFET and nFET devices, respectively. This uniaxial type of strain is optimized to exert strain primarily in the direction along the channel. Because these liners also function as etch stops for the contact etch, this approach, when used on both transistors, is called a dual etch-stop liner (dESL). Figure 2 shows the stress directionality in pFET and nFET transistors for bulk silicon and SOI. Presently, highly tensile stress liners for nMOS devices are available, and highly compressive stress liners for pMOS devices are under development. The main drawback to stress liners is the dependence on geometry, including gate pitch (which is smallest for nested transistors). With stress liners, “the key is achieving conformality of the film without pinching off the top, because as you go to smaller geometries, you want the nitride to go around the LDD spacer and be able to contact the silicon on the bottom,” said Farhad Moghadam, senior vice president of Applied Materials. To accommodate these real-estate limitations, the nitride film has to be made thinner while maintaining high stress. The process integration challenges involve having a good contact liner etch, with selectivity between the nitride types and to the silicide. In addition, since the tensile and compressive liners overlap, the boundary between the films must be carefully optimized. In the end, ~40-60% of the original stress is transferred to the channel by liners.²

2. The stress configurations created in strained SOI and bulk silicon substrates. (Source: Freescale Semiconductor)

Figure 3 shows the extendibility of dESLs as reported by IBM (Hopewell Junction, N.Y.).³ In this study, an enhanced dual stress liner, advanced embedded SiGe (eSiGe), stress memorization and advanced annealing were combined in a 45 nm SOI device to achieve drive currents of 1240 µA/µm and 840 µA/µm at 1.0 V, respectively.³

3. Strain enhancement realized using a dual etch-stop liner increased by a factor of 1.8× from the 90 to the 45 nm node. (Source: IBM)

Bart van Schravendijk, CTO of the dielectric business at Novellus (San Jose), said that hydrogen content in the compressive film on the pFET needs to be minimized as much as possible so that devices pass reliability testing, including negative temperature bias instability (NBTI). Tensile nitride films are optimized by combining plasma-enhanced chemical vapor deposition (PECVD) and ultraviolet (UV) curing on the same platform. According to Moghadam, this prevents film oxidation that occurs on exposure to atmosphere. Once formed, the oxide essentially blocks the curing process and thus limits the tensile stress levels that can be achieved. Because the UV cure would reduce the compressive stress of the nitride on the p-channel, the tensile stress film is deposited first. “With closely spaced gates, you can remove the spacers before putting the film down — using a thicker film without having the sides of the films touch each other, because if that happens, this reduces the strain,” van Schravendijk said.

Premetal dielectric films, deposited by PECVD, can also be optimized for stress level. Likewise, shallow trench isolation (STI) regions, typically somewhat compressive films, are being changed to induce tensile strain. “There is increasing demand for higher-aspect-ratio gap fill as geometries continue to shrink for advanced logic and flash devices,” Moghadam said. The process uses the same reactor as the previous STI films (sub-atmospheric CVD), but with TEOS and ozone precursors.

Moghadam said that other additional films are being evaluated, such as TiN, which is a likely candidate for the nMOS metal gate. “Studies have shown that a 50 Å TiN film can induce 10 GPa of tensile stress,” he said.

Another common form of process-induced strain is called stress memorization — similar to the liner technique, but the liner films are sacrificial. Stress is memorized into the device by depositing a film over the gate or S/D region, performing the dopant activation anneal, and then removing the film. This technique is more complex, and has mostly involved the use of nitride or oxide films to memorize tensile strain in nFETs. A key issue with stress memorization is achieving the desired nMOS performance enhancement without degrading pMOS performance.

But despite the increases in mobility that are attained, van Schravendijk warns that the series resistance may limit the benefit obtained. “Transistor optimization requires lower series resistance, which people are tackling by using optimized annealing sequences or, in some cases, more radical approaches like Schottky barrier devices with metallized source/drains,” he said.

SiGe epitaxy

A third common stressor approach involves etching out the S/D area and replacing it with a lattice mismatched material such as epitaxial SiGe in pFETs and, most recently, epitaxial SiC in nFETs. Because of the epitaxial deposition technique, the germanium or carbon atoms substitutionally replace silicon atoms in the lattice (rather than forming the compound SiGe or SiC). Germanium (5.66 Å) atoms are slightly larger than the lattice constant of silicon (5.43 Å), so SiGe on silicon exerts compressive strain on the silicon channel. Carbon has a much smaller lattice constant (3.56 Å), so silicon containing even a small amount of substitutional carbon exerts significant tensile stress on the channel.

While the SiC approach is still relatively new and unproven, the SiGe approach has been used in manufacturing on both bulk silicon substrates and SOI as early as the 90 nm node.

4. Mobility increase from eSiGe in the S/D regions is a function of germanium concentration and proximity to the channel. (Source: Applied Materials)

SiGe studies have shown that two factors influence the gain in drive current the most: the proximity of the S/D areas to the channel and the germanium concentration in the film. Using various approaches, companies have been able to reduce the space between the S/D and the channel, improving drive current (Fig. 4 ). The slope of the recess etch is also critical, and in situ boron doping is often performed. The sidewall spacer dimensions determine the S/D proximity to the channel, though sacrificial spacers and the like are being used. “You cannot create a lot of damage during the etch process or else you're setting yourself up for defects in the epi that is subsequently grown,” St. Dennis said.

There are other advantages to the eSiGe stressor, including the ability to retain hole mobility gains at high vertical fields and reduce device channel and extension resistance, which has a significant impact on the short-channel transistor drive current.² The improvement in extension resistance is caused by the ability to increase the active boron concentration in the S/D via in situ doping, while a compressive interlayer dielectric (ILD) stressor reduces channel resistance to improve hole mobility.

The process challenges associated with SiGe S/D epi include creating a defect-free epi region. “There's always a trade-off between how much germanium you put in and how much defectivity you introduce,” Moghadam said. SiGe film with 18% germanium can roughly induce 1 GPa of compressive stress (90 nm node), whereas at 20% germanium, 2 GPa is induced (65 nm); at 45 nm, 22% germanium is being evaluated.

5. High-quality, defect-free SiC (1.6% carbon) epitaxial film grown selectively in the S/D regions of an nMOS transistor. High carbon concentration and selectivity is achieved using a cyclic-deposition and etch (CDE) process. (Source: ASM)

Since the drive current of the pFET has been boosted sufficiently by the eSiGe and compressive nitride films, the nFET is now the rate limiter in terms of performance. This has encouraged companies to evaluate SiC, but the behavior is different from the experience with SiGe. “Germanium is completely miscible with silicon, whereas carbon has a very low solid solubility limit in silicon. As a result, a silicon lattice with a concentration greater than around 1% carbon tends to be one created at non-equilibrium conditions,” said Shawn Thomas, director of epi process technologies and applications at ASM International (Bilthoven, Netherlands). ASM recently changed to a new precursor for carbon doping, Silcore, which gives appreciable growth rates at a lower temperature (~450°C) than silane (Fig. 5 ). “It was not trivial to get selective, defect-free SiC to work from a materials perspective; now we are working with our partners on the process integration,” Thomas said.

“The substitutional carbon concentration is a key metric, and making this selective process work and then getting it through all the thermal cycles for the device has been a challenge,” said Gary Miner, CTO at Applied Materials. “When you are performing epi on a bulk wafer with blanket films, achieving high substitutional carbon is not a problem — it's when you need to integrate it selectively on a device wafer with different size openings with different surface orientations that the process becomes difficult.”

Strained SOI

Fully sSOI wafers, as well as strained silicon on SiGe on insulator (sGOI) wafers, build strain into the entire active area of the device. For strained silicon grown on a relaxed SiGe (20%) layer, a 1% silicon lattice deformation results in biaxial stress of 1.5 GPa. Mobility enhancement is primarily for the nMOS device, though with higher germanium concentration, pMOS improvements are possible.

In sSOI substrates, a strained silicon layer has been grown on a relaxed SiGe-graded buffer layer on silicon. Only then is the strained silicon transferred to the product wafer with the buried oxide region. Many years of development went into the commercialization of sSOI wafers by Soitec (Grenoble, France), announced last summer. Part of the issue was the desire for a germanium-free substrate. A key challenge with the epi was reducing the defectivity level — called threading dislocations — to an acceptable level for manufacturing. “When you relax the SiGe, dislocations form when the layer becomes thicker than the ability of the substrate below to maintain the strain energy of the film — you break some bonds between the germanium and the silicon, creating a misfit dislocation. These propagate in the plane of the wafer, and a threading dislocation is the vertical component of a misfit dislocation,” Thomas said, adding that threading dislocations contribute to device leakage current. During ASM's development with Soitec, the dislocation density has been brought down to 10⁵ defects/cm² for sSOI.

AMD, Freescale and IBM researchers have independently shown that the initial biaxially strained SOI substrates can be modified during device processing to achieve the desired uniaxial stresses to benefit nMOS and pMOS transistors.^4-6 Compatibility of popular process-based strained silicon techniques available to pMOS, such as eSiGe and ESL, have been demonstrated. This hybrid strain combination may provide an effective scaling solution to overcome the loss of effectiveness of ESL stresses when gate pitch is reduced to meet circuit density needs.

To take full advantage of the crystal-orientation dependence of carrier mobility, nFETs and pFETs need to be fabricated on (100) and (110) surfaces, respectively. For standard (100) substrates, the notch or flat is aligned along the &110> direction. By rotating a transferred silicon layer by 45°, transistors become aligned with the &100> direction, providing significant mobility enhancement for the pMOS transistors. One hybrid-orientation technique (HOT) involves transferring a (110) silicon layer onto a standard (100) substrate. A second (100) layer can be formed on top of the (110), and the nFET is built in the (100), while the pFET is built in the (110) layer.

But a HOT inherently introduces another level of complexity to the process. “Customers have HOT as a candidate technology going forward, but I don't know of a HOT device in a production product,” St. Dennis said.

Higher mobility channels

In addition to combining the various techniques already covered, people are examining the benefits of replacing the channel material with a higher-mobility material than silicon, such as SiGe or III-V materials.

Process extendibility

Though the scalability of stressor techniques is a concern, as far as the 45 nm generation goes, the fears have not been realized.

For instance, D.V. Singh and coworkers at IBM's T.J. Watson Research Center (Yorktown Heights, N.Y.) demonstrated stress memorization and dual stress liners in a fully depleted SOI structure with 25 nm gate lengths.⁷ They determined that stress transfer to the channel by stress memorization likely occurs through the poly gate, and becomes more effective as the thin body is scaled. Combining the dual stress liners and stress memorization techniques led to a net gain in drive current (~20%) that was substantially larger than that obtained using each technique separately.

The scalability of eSiGe S/D is not immediately apparent. Shrinking transistor active area reduces channel stress, but the SiGe region is brought closer to the channel, increasing stress. Applied Materials is working together with IMEC (Leuven, Belgium) and Synopsys (Mountain View, Calif.) to determine the effects of active-area dimension, channel length, S/D recess depth, germanium concentration and S/D-to-channel distance on pFET performance.⁸ Researchers considered isolated and nested transistor layout differences. Simulations determined that average channel stress could be maintained, even with a constant germanium concentration of 20%, from the 45 to 22 nm nodes.⁸

Biaxial strain methods may be the most scalable. “Uniaxial strain is very effective for short-channel devices, but with global strain, the same amount of strain is induced on the short-channel and long-channel devices,” Thomas said.

The metrology of strain

There is no direct method of measuring strain in the channel of a transistor. The germanium concentration, which is related to the strain, can be measured by X-ray diffraction (Fig. 6 ). Time-of-flight SIMS or X-ray photoelectron spectroscopy (XPS) can also be used. Another destructive method called convergent-beam electron diffraction using focused ion beam (FIB) prepared samples can measure the strain and stress in layers. “There has been work to go to smaller spot sizes with this technique, but essentially people just focus on the I_on/I_off data to look directly at drive current,” said Reza Arghavani, Applied Materials' Fellow. “In addition, the destructive techniques introduce error since the TEM prep milling makes the sample atomically thin, which can allow the strain to relax,” van Schravendijk said. Argavani explained that non-contact optical techniques can also be used, “but they cannot comprehend the small geometries that are used at 45 nm and beyond,” he said.

6. Different concentrations of Si1-xGex and Si1-yCy epi films used as pMOS and nMOS S/D stressors, respectively. Interference fringes indicate high crystalline quality. (Source: ASM)

Conclusions

Compressive nitride and eSiGe S/D stressors combine well to optimize pFET mobility. Tensile nitride stress liners and stress memorization have primarily been used to optimize nFETs. Companies that are using partially depleted SOI substrates are benefiting from sSOI with careful process optimization. The choice of stressors will largely be dictated by cost-effectiveness and production-worthiness of the stressor techniques as more advanced approaches begin entering the fab environment.