Advances in SOC Fuel Growing Markets
Ruth DeJule, Associate Editor -- Semiconductor International, 4/1/2000
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At a Glance |
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As the complexity of advanced semiconductor devices escalates and time-to-market pressures heighten, system-on-a-chip (SOC) is meeting the demand and fast becoming the industry's latest buzzword. Included in the 1999 Roadmap, SOC technologies combine memory and logic, analog and digital on a single chip with targeted gate counts in the millions (Fig. 1). More than application specific ICs (ASIC), typically one chip for one application, SOC draws market share away from existing markets. By 2003, the SOC market is expected to nearly triple to $15.7B, according to market analyst Semico Research (Scottsdale, Ariz.). And despite non-recurring engineering costs approaching $1M, eight times higher than that of classic ASIC devices, a 38% cumulative average growth rate (CAGR) is anticipated over the next three years. Behind the surge in SOC are a new philosophy and strategies based on reusuable IP that are turning out prototypes in a matter of months.
 1. Projections indicate a significant rise in SOC total available markets (TAM) over the next two years, with cellular handsets leading the way. (Source: DataQuest) |
Beyond ASIC
System-on-a-chip and system-level-integration (SLI) often are used interchangeably, though some view SLI as more of a process and SOC more as a philosophy. For others, SLI is the sum total of SOC plus application software. Whatever the perception, the end result is a system contained on a single piece of silicon, made possible through a combination of advanced electronic design automation (EDA), silicon process technologies, intellectual property (IP) cores and packaging.
Driven by phenomenal cost, SOC applications typically are high volume. Considerable cost pressures can be seen even in the high-growth wireless industry, with the first movement of total available market (TAM) in SOC toward these high-volume applications. This moves the lion's share of the revenue stream from classic ASIC to SOC, though the transition is more than a simple case of the ASIC market evolving to SOC. SOC is, by definition, the integration of the processor, ASIC and the communication peripherals, and even some analog in a single chip. SLI consumes not only the ASIC market but that of the processor and communication peripherals, and edges into the mixed-signal space. The integration of multiple functions results in significant added value. Therefore, going from classic ASIC to SOC is more than moving boundaries; SOC feeds off multiple markets, giving it more opportunity for growth. This year, SOC designs may comprise up to 55% of the ASIC market, according to DataQuest. Integration can reduce size, number of components, power consumption and cost of ownership while increasing reliability.
Integrating technologies
The microprocessor is fundamental to classic SOCs in the operation of the application, whether a mobile phone or hard disk drive, a PDA or a set-top box. Embedded memory, random logic and mixed-signal complete the SOC. Embedding SRAM (static random access memory), DRAM (dynamic) and NVRAM (non-volatile) with logic devices have all been demonstrated , although currently only embedded SRAM is widely used. The basic storage element in an SRAM is a transistor, remaining in one state until it is switched. This is consistent with logic devices, minimizing fabrication challenges for embedded SRAM. However, one bit of SRAM memory requires six transistors, consuming valuable chip real estate. SRAMs may therefore be economical for low-memory requirements, but become costly for memory over 1Mb.
DRAM packs more memory into a small space, one bit of DRAM requiring only one transistor. The basic storage element in DRAM is a capacitor, making integration with logic devices difficult and costly. By one estimate, embedded DRAM fabrication uses the first 40% of the process flow of ~300 steps in making the capacitor. To address these concerns, IBM, Infineon and Toshiba formed a consortium to develop embedded DRAM technology, and the results were good. "Today many systems using 0.14 µm gate technology have millions of gates on chip with 64Mb of embedded DRAM, but using SRAM at the same die size would avail only 5 or 6Mb of memory," stated Peter Richmond, director of business development in SIC at Toshiba's system integration division. Cost becomes less of an issue for large-memory applications(>128Mb) such as switches and routers in networks, disk drives, controllers, set-top boxes and graphics, he said.
 Systems-on-a-chip can integrate a variety of functions including logic, memory, and analog and digital capabilities to meet the demanding requirements of today's exploding communications applications. (Source: LSI Logic) |
Embedded mixed-signal technologies provide connection to the physical, analog world, and serve the rf and wireless market, video encoders, and high-performance digital-to-analog converters. Low freqency DSPs using CMOS combines analog and digital. "Currently, SOC does not have a solution for everything, in particular higher frequency and higher bandwidth required by some wireless applications," stated Sal Mastroianni, vice president of technical staff at Motorola. Thus, the need for technologies such as BiCMOS continues. However, progress is being made. Three years ago, Samsung took a step forward by developing a metal insulator metal (MIM) process as a cost-effective alternative to traditional double poly processes. By sandwiching isolation layers between metals 1 and 2, resistors and capacitors can be built while providing a model that is very similar to the digital model. The analog block therefore can be connected easily to the digital design for design verification and analysis.
Intellectual properties
More than proprietary technologies in the form of patents, to a large extent IP is concerned with implementation of standard connection interfaces -- for example, those typically found in computers, PCI sockets, Firewire and PCM CIA cards. Some are unique to telecom applications, others to cell phones. The actual implementation of the IP in a particular process technology is critical. IP such as the ARM and computer processors are widely used, so they've become a defacto industry standard.
Initial patent licensing fees to companies like ARM Limited may run from tens of thousands of dollars to a few million. But most major semiconductor companies have created their own IP and have fairly robust IP portfolios. Mixing IP from various sources, however, becomes very difficult, for the blocks don't necessarily fit together. To facilitate the integration process, consortia and organizations such as Virtual Socket Interface Alliance (VSIA) and Design Reuse and Virtual Component Exchange (VCX) are driving the definition of virtual components. VSIA's nearly 500 corporate members are trying to establish standards to increase interface compatibility among countless SOC designs, from booting the operating system to running test applications. VCX offers another service by facilitating the trade of virtual components among its members, working to create a web-based trading environment. The goal is to register buyers and sellers, and list and license virtual components in a simplified, industry-defined process.
Reusable IP
Behind Texas Instruments' roadmap to improve DSP performance 15X over the next five years are design strategies revolving around the concept of reusable IP or virtual components. In the early 1990s companies were typically organized by product capabilities, such as ASIC, digital signal processing (DSP), memory and analog, targeted towards particular product and application segments such as DSP for wireless handsets. Today, they are organized by market segment or application focus, such as networking, wireless and computing products, which can leverage multiple capabilities into a system chip, noted Tony Parker, ASIC product line manager at Lucent Technologies. As the need to merge IP across different application markets evolved, it became apparent that proess compatibility would play a key role in enabling IP reuse without redesign. The end result is that all business units create IP in a common process, which can be easily shared and reused across business units and customer applications, he said.
Companies such as Actel, Altera and Xilinx have created prototyping vehicles such as field programmable gate arrays (FPGA) that allow fabs to download a circuit and a standard layout that essentially will meet the circuit's requirements. Philips' Rapid Silicon Prototyping, for example, creates virtual components that can operate with FPGAs. Compared to simulation, this means 10,000X more experience with the design before going to final silicon, according to Robert Payne, vice president of system ASIC technology at Philips Semiconductors
 2.SLI Architect selects IP modules and assembles them along a common VBUS to produce a first-pass sub-system in a couple of hours. (Source: Texas Instruments) |
Critical to SOC is taking the IP modules and connecting them in an efficient way. Texas Instruments does this by having a common bus architecture called VBUS which essentially "bolts" the IP modules together. (Third-party IP typically requires additional interface IP for standardized interface.) SLI Architect allows TI to select IP modules from their repository and assembles them in an automated fashion (Fig. 2). Thus, a customer can create a first-pass processor subsystem in an hour or two and initial verification in 1 to 2 weeks, instead of 1 or 2 months.
Design cycle times
Once the predefined IP blocks have been assembled, the design must undergo functional and timing verification, both time-consuming tasks. For geometries &0.35 µm and with gate counts in the millions, timing closure -- the verification that each gate performs in a specified amount of time -- has become critical. Timing closure relates back to the EDA tools, the design stage. When an ASIC is designed, the customer begins with an architectural concept for the system, develops a behavioral model describing how the intended chip will work, and synthesizes the model into a netlist, a written description or schematic of the chip. The ASIC vendor works with the netlist and translates it into a physical layout of the chip. Three years ago, the type of technology -- the design rules -- didn't significantly affect the design in terms of the layout process. This is not true in today's 0.15 µm technology. At layout, unknown parameters such as nanosecond delays are introduced, then fed back and forth between customer and vendor until the layout conforms to the design. For classic ASIC, the design cycle may extend from several months to a year.
Today, SOC manufacturers have created strategies to address timing closure and reduce cycle times. For example, LSI Logic's FlexStream design environment provides single-pass timing by closely linking the logical and physical design, and taking into consideration parasitics. Placement of IP blocks takes place at the RTL level so that timing information can be extracted very early in the design flow. Verification times can be reduced through a combination of functional verification of IP blocks, hardware/software co-verification that allows software and hardware to be developed in parallel, and the use of embedded FPGA technology that allows critical logic paths to remain flexible and undefined to final prototyping.
IBM's SuperStructure methodology provides customers with preconfigured, pretested base model chips that contain required features for a particular application. Customers can add their own IP, eliminating the need to design an entire chip from scratch and thereby accelerating time to market.
With design schemes such as Toshiba's Timing Driven Flow, the tools needed to predict what will happen at layout are in the customer's hands. So instead of months of iterations, "we've seen customers reduce design cycles down from one year to several months (Fig. 3)," asserted Richmond.
 3. As average gate counts increase, strategies that reduce design iterations are holding engineering cycle times to under four months. (Source: Toshiba) |
Lucent also has developed application specific design platforms that accelerate time-to-market. For example, Lucent's GSM platform design includes flash memory that is easily programmable, instead of ROM. They embedded 150,000 gates with a laser-programmable gate array that can be turned around in less than one week. Lucent provided the development tools and software support for embedded IP such as the ARM core and DSP core. In production, the FLASH code is converted to a ROM code, which is more dense, and the LPGA block converted into a standards cell, also more dense. Instead of months, the design was turned around in weeks.
System-in-a-package
Embedded DRAM and embedded NVRAM with microprocessor and analog interfaces are feasible and even in production. But beyond feasibility, many raise the question of economics. When added together, is it possible to produce a $4 microprocessor with its associated subsystems, practical for a $50 cellular phone? Cost analysis at Motorola indicates embedded DRAM may cost between 2X and 3X more than bringing together commercially available commodity components onto one package. An extension of multi-chip modules, system-in-a-package (SIP) combines, for example, a microprocessor and a stand-alone 2Mb DRAM or silicon control logic and analog interface with GaAs devices optimized for rf and wireless, thus providing a complete solution as the end user would see it (Fig. 4). Replacing ceramic packages with lower-cost organic materials and designing devices with lower power consumption may significantly reduce total cost to $10 or $15/module, according to Motorola. Currently, however, there is no design methodology that concurrently takes into account components from dissimilar technologies and no test and repair technologies.
 4.A conceptual view of a fully integrated microwave/RF/IF system displays a high-frequency system in a single package. (Source: Motorola) |
Although SIP lacks the development of SOC, in some respects, it may be serving as an interim solution or an economic alternative. Open an Intel microprocessor, and you'll see a module containing both the microprocessor and associated memory. In the future, memory devices may turn to SIP as an enabler to system integration. Some of the new high-k gate materials such as tantalum pentoxide require high-temperature oxygen anneals to improve memory capabilities. Insurmountable SOC challenges may be confronted because of the degradation caused by subsequent forming gas anneals needed for logic device processing. Due to such manufacturing challenges, SIP may offer a more viable total system than SOC.
What's ahead?
 5.Current design tools may soon lag behind process technologies, creating a need for new technologies to meet expanding design cycles times. (Source: NEC) |
SOC has come on in full force in the last couple of years. Tool vendors such as Cadence Design Systems (San Jose, Calif.) have developed the design framework that allow simultaneous integration of different functions such as memory, DRAM and microprocessors. What are the limits of SOC? Lucent's COM-2 technology has demonstrated a 1.5 V design in a flip-chip package with over 12Mb of memory and 2.5M gates; integrating 100,000 gates/mm2 with 0.16 µm technology; increasing density by an order of magnitude higher than two years ago at the 0.35 µm node. But as gate counts move into the tens of millions, it could take thousands of man hours to build a fully functioning design using current design methodology. Some see this as a growing gap between improvements in process technology and design expertise (Fig. 5), calling for new design strategies such as NEC's ACE-2, intended to reduce turnaround times by two-thirds by focusing on a higher level of design abstraction. NEC is targeting three-month turnaround times for 30M gate SOCs by 2002. After a slow start, SOC is progressing rapidly, meeting the increasing demands for increased memory and size reduction. •
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Meeting the Needs of SOC Test Systems
Eric Larson, Product Manager, Teradyne |
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Testing integrated circuits that combine multiple functions on a single die is not a new problem. Economics dictate that these SOC devices be tested in a single insertion, as multiple passes on different automated test equipment (ATE) adds cost. Thus the need for complete SOC test systems.
Keeping up with the demands of SOC poses several challenges for the test industry. Digital test capability is one of the biggest. One measure of a test system’s digital capability is the number of signal pins it can handle when interfacing with the device. As device gate count and complexity increases, so does the number of signal pins. Typical gate counts today are under 300,000, but this number is expected to rise to well over 1M gates in the next year. Although they require state-of-the-art mixed-signal and embedded memory test capability, most SOC devices today are still under 300 signal pins. Devices requiring higher pin counts generally are pure “digital” devices and can be tested easily on high-end digital ATE. Next-generation SOC devices are changing the rules, integrating the highest-performance mixed-signal cores into today’s pure digital devices. Just like the single-insertion requirement above, test economics require that multiple devices be tested in parallel. To ensure proper test coverage and full utilization in production, 1024 pin ATE with memory and mixed-signal capability is needed. ATE frequency, accuracy and vector depth, which scales directly with the number of instructions and clock cycles executed during testing, also are key to the effectiveness of SOC test. With standard busses such as PCI running well over 100MHz and AGP4X at 266Mbps, SOC test systems must be capable of very high, sustained data rates. Specialty interfaces such as Low-Voltage Differential Signaling (LVDS) soon will push ATE frequency requirements beyond 500Mbps and edge-placement accuracy down below 100 picoseconds. Despite the best efforts to design in testability, million-gate devices are driving hard on vector depth needs. Broadside requirements are moving from the current 8M standard vectors to 32M or more, while serial scan vector depth and width is growing even more rapidly. Chips are being designed today with literally dozens of scan chains, each requiring nearly 60M vectors to test. Mixed-signal capability remains critical for the future of SOC test. Mixed-signal IP cores are available from a seemingly unlimited number of design houses. These cores can show up anywhere, on any device, and in any quantity. While by no means perfected, the ability to stitch together IP cores into a single chip gives anyone in the world with skill and a workstation the tools to create multi-million-gate, mixed-signal systems-on-a-chip. Ultimately the SOC test system must be faster and better than the ICs it is testing. It must stay ahead of the technology curve, both digital and mixed-signal, shifting away from old test paradigms to new test solutions. This is not an easy challenge, but it must be met in order to address the SOC revolution. • |
Actel www.actel.com
Altera www.altera.com
ARM Limited www.arm.com
Cadance Design Systems www.cadence.com
Xilinx www.xilinx.com
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