Litho Guru Optimistic About Nanoimprint
Laura Peters, Editor-in-Chief -- Semiconductor International, 4/30/2008
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Ben Eynon, Director of Advanced Technology Development at Samsung (Seoul, South Korea) and Associate Director of Lithography at Sematech (Austin, Texas), discussed Samsung’s evaluation of nanoimprint lithography at the SEMI Strategic Business Conference (Napa Valley, Calif.). “The resolution is there for sure, it’s a matter of the defects and throughput,” he said. Interestingly, nanoimprint actually improves on one of the metrics that extreme ultraviolet (EUV) struggles with: line edge roughness (LER) and linewidth roughness (LWR). After etching, features printed by step-and-flash imprint lithography actually produce smoother features than before the etch. Eynon showed impressive results (first released at the SPIE Microlithography Conference). He said that companies may choose to implement different lithography technologies depending on particular product mix.
Eynon also provided an update on the challenges that EUV lithography has yet to overcome. “We look for the weakest link in going from ArF to EUV.” These include development of photoresist, autofocus, pellicle, reflector, absorber, optics, debris mitigation, a vacuum processing environment, mask handling, mask haze, shadowing and chucking. Then, once EUV is established in high-volume manufacturing, taking it to the next level will involve the usual additions of high-numerical-aperture (NA) optics, phase-shift masks, optical proximity correction (OPC), etc. Among these, the top challenge (Table) is developing a source with adequate power — at least 100 W is necessary. One of the candidates for the high-index photoresist that Sematech is testing is hafnium oxide nanoparticles suspended in water — although the shelf life of this material is not encouraging. Mask blanks with 0.04 defects/cm2 at 53 nm have recently been achieved, a big breakthrough according to Eynon. A new reticle inspection tool (M7360), priced at $10M, is allowing researchers to see even smaller defects than was possible with the previous-generation tool. In addition, a smoothing process has been developed — a deposition and etch process that can smooth, for instance, a 50 nm pit to 1 nm in dimension. “With this smoothing method and other techniques, we can get to the point where we don’t need completely defect-free masks, but can have a manageable level for manufacturing,” Eynon said.
At the 2008 Litho Forum, hosted by Sematech, participants will vote on the most likely technology to meet the high-volume production needs of the 22 nm node. When the group voted in 2006, EUV was unanimously chosen as the technique of choice for 22 nm in the year 2012. Unfortunately, even Intel (Santa Clara, Calif.) admits that EUV will not be ready for 22 nm, so immersion lithography with high-index materials or double patterning will have to come into play.
Stay tuned for our coverage of the Litho Forum.
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most of the comments are people trying to sell something (by knocking the competition) except the first one. As for that one, I don't think EUV priorities drop from 1st place because they're solved but because after a while, people realize other issues are more difficult than previously thought.
trr - 6/11/2008 5:58:00 PM CDT -
I checked the Obducat photo. Some of the dots are missing...
reader - 5/2/2008 2:45:00 PM CDT -
Obducat secures HDD industry roadmap
Obducat has concluded the development of the capability to simultaneously imprint both sides of the hard drive substrate.
Obducat has also proved the ability to imprint 17nm features with its proprietary IPSâ„¢-STUâ„¢ process.
Furthermore, 17 nm dots have been printed uniformly with a residual layer below 7 nm. The capacity of the Sindreâ„¢ HDD high volume manufacturing system targets the requirements of the hard disk industry having a throughput of 1200 disks/hour.
Cane Corso - 5/2/2008 1:46:00 PM CDT -
From Kozawa et al. we have:
freed electron + acid generator -> dissociated products
The freed electron comes to a stop before reacting, otherwise it would be too hard to catch, so to speak.
This affects the direct use of ionizing radiation (X-ray, EUV, ion, electron-beam, two-photon, etc.) in lithography. This would also affect how the nanoimprint template is formed if using electron-beam lithography.
Nanoimprint layer support is also affected by the porosity of low-k porous materials, which makes them softer.
Phase change memory structures today have no time to wait for new lithography techniques. They have found other ways to far exceed the resolution limit of lithography.
senior researcher - 5/2/2008 2:16:00 AM CDT -
Implant Litho: Yes, resolution is there... so as X-ray, e-beam, ion beam… and other atomic manipulation litho techniques… but what about making/inspecting/repairing 1X mask which must to be rubbed against wafer every time it “prints� What would be the lifetime of such a 1X template? To keep up with demand of microelectronic chips needed, it would need to print at 200,000 stampings a day! Assuming excellence in engineering would solve alignment, printing on topography, defects… etc. challenges. How many of these masks will be needed to keep up with chip demand?
Won Kim - 5/1/2008 2:41:00 AM CDT
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