Memory Test Platform Handles Multiple Device Types
Verigy's newest memory test family handles flash, DRAM and multichip packages (MCPs) -- at the price of a flash tester.
Sally Cole Johnson, Contributing Editor -- Semiconductor International, 11/26/2008
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| Verigy’s V6000 is scalable across the entire semiconductor memory test process, including engineering, wafer sort and final test. |
Responding to industry demand for a memory tester with the flexibility of testing flash, DRAM and MCPs, Verigy (Cupertino, Calif.) has unveiled the latest addition to its portfolio, the V6000 family, which encompasses engineering, wafer sort and final test.
Price erosion in the memory market and test costs that haven’t come down as much as the semiconductor industry would like, combined with increasing memory bits, are creating challenges for automatic test equipment (ATE) manufacturers. “Test requirements are increasing each month, relative to the number of bits that need to be tested, and this creates flexibility challenges for our customers,” said Gayn Erickson, vice president and general manager of Verigy’s memory test solutions. “Years ago, there were flash manufacturers and DRAM manufacturers — no one built both. Today, everyone is building both. Now they can test both on the same tester. Our V6000 family scales from engineering, wafer sort, to final test applications on a single platform. The system has up to 880 Mbps test capability and is actually the highest parallel test system ever introduced.”
The V6000’s wafer sort can do 300 mm single-touchdown probing for flash or DRAM, with scalable performance up to 880 Mbps, as well as scalable parallelism up to 18,000 I/O pins and scalable probe cards.
And the V6000’s final test is designed to test flash, DRAM and MCP devices. The tester and test cell scale to any device with scalable parallelism up to 18,000 I/O pins, Erickson said, and offer single-insertion testing of MCPs.
With test requirements changing so rapidly now, scalability is becoming critical — especially in the field. “A memory test system you can buy at different data rates is unprecedented in this space,” Erickson said. “The same tester can be purchased at 140-880 Mbps and be upgraded in the field to increase speed, performance and signal fidelity, while reducing test times and improving yields associated with those performance and price points.”
You might notice that the tester head is somewhat unconventional in shape, and the reason is form following function. “The test head was specifically designed around the challenges of meeting massive parallelism without compromising the performance needed to test both flash and DRAM devices at both wafer sort and final test. The result, in fact, is that the V6000 delivers uncompromised signal integrity due to a dramatically shortened signal path to the pin electronics — and to the wafer or device under test (DUT),” Erickson explained. “For example, to test 768 DUTs in package form, the devices cover a very large rectangular array in a high-parallelism device handler. With the V6000 architecture, we’re able to place the test system’s pin electronics right next to the DUT, even though it covers an area larger than 1 m across. In the wafer test configuration, we’re able to arrange the pin electronics in a small radial array that brings all 18,000 channels to within inches of a 300 mm wafer. We’ve designed the test system so that it doesn’t degrade the testing performance across two significantly different applications with vastly different area arrays. Our test system electronics and mechanical integration and design allow us to uniquely meet the challenges of testing both final test and wafer-level test on the same platform without compromising parallelism or performance.”
The test system’s size is another noteworthy point. Its performance in one system displaces four of its competitors’ machines, according to Erickson.
Numonyx (Rolle, Switzerland), which manufactures a full range of memory technologies, has already selected the V6000 for high-volume wafer sort of its NAND devices and known good die, based on the platform’s parallelism, performance and low cost-of-test.
Outlook for memory test
The memory test market may not look too hot right now, but it could snap back quickly once demand for memory chips picks up again. That said, market research firm Gartner (Stamford, Conn.) is revising its memory test forecast in mid-December, and the market is in a much steeper decline than previously expected — on the order of 55-60% this year. “It’s going to be about 10 percentage points worse than we originally forecasted,” said Mark Stromberg, principal analyst at Gartner. “This is a substantial decline, with total memory test sales in the $600M-700M range.” The $500M-$700M range is where you really begin bleeding capacity out of the system, because you can’t even keep up with the basic replacement level for various technologies, he added.
The outlook for memory test doesn’t improve much for 2009, either. “For 2009, we were looking at a very slight decline of about 5%, but now it looks like it’ll be closer to 15-20%,” Stromberg noted. “We don’t expect to see a significant turnaround in memory before the second half of next year, and that’s in line with what we’ve been hearing from industry players in Asia. Obviously, if that gets delayed by a quarter or so, it’ll essentially be 2010 before we see any significant move in the memory market.”
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