E-Beam Technology Breaks Through Complex Design Cycles
Rising fabrication costs and increasingly complex design cycles are making electron-beam direct write (EBDW) more appealing for an expanding range of applications, including prototyping and ASIC production.
Haruo Tsuchikawa, Masaki Takakuwa, Shinji Sugatani and Takashi Maruyama, e-Shuttle Inc., Kawasaki, Japan -- Semiconductor International, 2/1/2009
Rapidly rising costs and increasingly complex design cycles for advanced standard cell and system-on-chip (SoC) devices have forced many potential foundry customers into postponing or canceling projects. Often, they make the decision to seek alternatives such as FPGA prototyping to initiate their designs.
Fab costs have risen for many reasons as process geometries shrink. Higher reticle prices and other factors have had a measurable impact. Total costs in 2005 averaged $1M for a 10-million-gate design using 90 nm process technologies. Today, 100-million-gate designs at 65 nm cost almost twice as much.
But there is an alternative that can reduce the high costs of materials and processes for custom designs, and encourage a larger number of the starts that are often delayed or cancelled. Electron-beam direct write (EBDW) capabilities, which are available for prototyping and low-volume production, candefine pattern geometries with extremely high fidelity, and the e-beam patterns once defined can be overlaid to various layers with high degrees of accuracy.
E-beam characteristics
Because electron beaming is a computer-controlled sequential process, no pattern masters are required. E-beam writes transfer design data directly onto the resist-coated wafer and exposes it, so there is no need for masks (Fig. 1). Pattern generation is direct and flexible. This eliminates delays caused by mask production, as well as the need for optical pattern correction.
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| 1. Unlike optical lithography, which uses increasingly expensive masks, e-beam lithography transfers design data directly onto the resist-coated wafer and exposes it. |
E-beam lithography draws patterns with more fidelity than photolithography. A square pattern, for example, is drawn by e-beam as a square form, while photolithography creates corner rounding patterns, like a circle. The mask pattern is then modified for e-beam to correct as an octagonal form, to approximate the circle shape. This modified pattern is almost the same as the original square pattern in photolithography.
The ability of e-beam technology to deliver these results comes from improvements in the equipment, process and materials now available for application. For example, better wafer stage motion, which is achieved by controlling the leveling table of a wafer stage in a stepper, enhances the accuracy of beam measurement. Improvements in beam calibration and stability, along with the high accuracy, are in place and proven. Mechanical parts, such as the body structure of the stage chamber, have evolved to meet the demands of deep submicron process technology.
Another challenge involves the efficient extraction of blocks using partial batch exposure. The e-beam direct writer can now be equipped with the character projection function called "block exposure," in which repeating patterns are made into a stamp, and then written with a beam. Block exposure involves 12 sets with 100 kinds of characters. Exposure speed is achieved by reducing the exposure shots to a rate of 0.36, which is obtained by applying block exposure to SRAM, ROM, repeated via, and so on. One-dimensional variable length block exposure obtains enough CD control when used in a 65 nm process. The method defines the beam width with stencil mask aperture size, so the size of the fine beam is stabilized at high levels. These results — in terms of linearity and high-voltage difference to the range of 60 nm widths — cannot be achieved using variable shaped beams.
Boosting EBDW throughput
A considerable challenge for e-beam lithography has been concerns about throughput. EBDW throughput is indeed almost 100? lower than optical lithography throughput, and deteriorates as miniaturization progresses and integration improves. Block exposure reduces the total number of shots and doubles or even triples throughput, and block exposure's efficiency is not linked to pattern size. To maximize efficiency, block types must not increase when register transfer level (RTL) coding is replaced with the physical layout. This requires standardization of cell height, shape, and power and grounding rules. Within those constraints, significant throughput enhancements are available.
Proximity effect correction is critical as well — at 65 nm, optical proximity correction (OPC) is essential to draw a mask pattern precisely.
Backscattering electrons from the substrate with multiple interconnect layers deteriorates the resolution of a high-density pattern. For 65 nm devices, the impact of backscattering electrons has been estimated in order to deduce the tuning parameter in the model. The result is sufficient resolution for the high-density pattern.
One major contributor to the efficacy of EBDW now involves improvements in computational technology, which help to enable the highly precise calculations required for proximity effect correction.
Cost benefits of EBDW
The benefits of e-beam lithography are illustrated by reviewing reticle costs, which are 6× higher for designs built using 65 nm process technology than they were at 130 nm. At 45 nm, reticle costs will escalate to 10× the cost of 130 nm.
The most expensive part of the 65 nm reticle set — which can reach a cost of ~$1.5M now — is the interconnection layer. Writing all fine layers with EBDW lithography instead of optical lithography could save 60% of the total reticle cost (Fig. 2). Replacing the front-end-of-line (FEOL) reticle with e-beam lithography could reduce the total turnaround time, also impacting cost positively.
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| 2. Writing all fine layers with EBDW lithography instead of optical lithography could save 60% of the total reticle cost. (Source: Fujitsu) |
Eliminating the reticle-making task saves time as well as cost, since reticle development generally requires two weeks or more. Once a lot is "in," more costs are reduced because pattern correction and data formatting can be completed in a day. This saves time and the resources typically needed for design-rule checking and OPC verification, which are required with typical photolithography methods, but are not needed with e-beam technology (Fig. 3).
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| 3. E-beam lithography realizes overhead reduction through the elimination of maskmaking, which typically takes two weeks or more. Time and cost are also saved as pattern correction and data formatting can be completed in a day. |
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| 4. More than two-thirds of ASIC designs require mask re-spins. (Source: Mentor Graphics) |
E-beam technology also can simplify IC re-spins, which are required in more than two-thirds of all ASIC designs (Fig. 4), and almost always add significantly to verification tool costs. E-beam is easy to adapt for re-spins because it can be used in prototyping.
Because the throughput of a single e-beam machine is not fast, it is best to use e-beam lithography for the lower interconnect layers with finer line patterns, and use photolithography for the coarser metal layers. In all, this dual method takes almost the same cycle time as optical lithography.
Using e-beam for prototype wafers
Typically, chip manufacturers develop prototype wafers at a small-scale production line or minifab, and then move them to a volume production line. Using traditional lithography techniques, this process involves a series of steps beginning with reticle mask development, then moving through potentially long sign-off processes, with design-rule checking and other typical requirements.
E-beam lithography can handle 65 nm prototype wafers. The prototype e-beam patterns can be transferred quickly and efficiently to photolithographic patterns, reducing total design time and load to a single week for many designs. No additional changes are required except for the switch in the lithography process. This enables easy site-by-site trimming of wafers. And, because mask set costs are shared, total costs are lower.
Time-to-prototype depends on total process turnaround time, not just the e-beam writing process. Since EBDW eliminates the maskmaking period, using e-beam for critical layers takes almost the same amount of time as an optical process. In the cases where a redesign is required, e-beam is much faster.
EBDW technology has been implemented in the e-Shuttle program co-developed by Fujitsu and Advantest Corp. The shuttle capability enables the development of many different designs on a single wafer, without adding processes, and employing a limited menu of two or three types of interconnect layers. The e-Shuttle concept with EBDW saves costs because it reuses reticle sets rather than disposing of them after each development process. Users can deploy multi-project reticles and realize the savings from eliminating the need for new reticle development for each activity.
E-Shuttle targets custom chips. Many users produce prototypes with FPGA devices or programmable logic devices (PLDs). However, if a customer requires a higher-speed or higher-density chip, these devices cannot satisfy their requirements, making the e-beam service attractive. In most instances, a single wafer will be used for a customer, rather than the shuttle service.
Several technological improvements in materials and equipment that are now underway will enable broader successful application of EBDW. Improvements in throughput, for example, will enable e-beam to expand its market potential. At a throughput of 0.5–3 wph, EBDW tools are appropriate for IC prototyping and have a market size of ~$94.32M. Throughput of 3–30 wph enables small-volume or mid-size production of ASICs and/or MOS logic, for example, with a tool market size of $282.94M–$1.89B. With a multi-column system, throughput could reach 30–100 wph, and maskless technology would have the potential to replace extreme ultraviolet (EUV) lithography at mass production levels. It is also very likely that EUV and EBDW could work together on SoCs, with EBDW used for all custom sections of a device and EUV applied to the standard portions.
Summary
E-beam lithography can reduce turnaround time and lower total costs, enhancing custom IC prototyping and encouraging design starts that are now being postponed or cancelled. This is a particularly effective technology for small-lot manufacturing, which can be restructured by adding the e-beam capability to a megafab.
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