Progress in Copper: A Look Ahead
Peter Singer, Editor-in-Chief -- Semiconductor International, 5/1/2002
| At a Glance |
| PVD-deposited diffusion barrier and seed, combined with electroplating, will continue to be used for at least one or two technology generations. Ironically, one of the main reasons for going to copper — improved reliability — has proved illusive. |
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Sidebars:
Defect Forensics in Electrodeposited Copper |
Copper has many benefits when compared with aluminum: It has better conductance (lower resistance), which means lines can be smaller and packed more tightly, yet still carry the same current. This translates into fewer levels of metal and lower production costs. Lower resistance also leads to faster speed. Also, copper has better resistance to electromigration, leading to improved reliability. Perhaps best of all, copper is said to provide better yield than aluminum-based devices of the same design.
Over the past five years, many semiconductor companies have moved to take advantage of these benefits, and copper is now in volume production at facilities around the world.
The move to copper, however, has not been without its challenges. The biggest change has been that, because copper is difficult to etch, an alternative patterning methodology called dual damascene is required, where trenches and holes are cut into the dielectric and filled with copper.
Copper is also a known fast-diffuser that can "poison" transistors. Steps must be taken in the fab and on the chip to prevent copper contamination. In the fab, this has led to separate copper areas where, for example, different colored cleanroom garments and wafer cassettes are used. On the chip, the copper must be encapsulated in "diffusion barrier" films, typically tantalum/tantalum nitride and silicon nitride.
Today, at the 0.18 µm technology node, copper processes appear to be relatively well understood and reproducible. Typically, the vias and trenches of the dual-damascene approach are created with a "via-first" strategy. This is followed by the deposition of a PVD-deposited TaN diffusion barrier and a PVD-deposited copper seed layer. The bulk of the copper is then deposited by copper electroplating (also called electrochemical deposition, or Electrofill by Novellus). This is followed by a planarization with chemical mechanical polishing (CMP), which brings the top of the copper lines and vias down to a level equal to that of the dielectric material that separates them. Another layer of dielectric is deposited and the whole process starts again, up to six or seven levels of metal.
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Applied Materials' Black Diamond process and Producer CVD system enables reliable, cost-effective integration of low-k dielectric into copper interconnect structures. Cover image: Applied Materials; SEM of multilevel copper/low-k dielectric device courtesy of TSMC. |
Looking down the road to the 0.13 µm and 100 and 65 nm technology nodes, the biggest challenges will most likely be integration issues. Not surprisingly, a successful copper process requires a wide variety of processes and technologies — dielectric etch, cleaning, barrier and seed deposition, electroplating, CMP and metrology — to work in perfect harmony. For instance, a dielectric etch process that leaves a slight undercut on the via, or a post-etch/pre-diffusion barrier clean that leaves residue or sputters copper up onto the sidewall, will almost certainly lead to microvoids in the copper. Such microvoids and other defects are a severe long-term reliability problem, because they can lead to delamination and high via resistance. The Table lists common defects and their sources, and Figure 1 shows common problems in a copper interconnect.
The addition of low-k dielectrics will also create a host of integration challenges. Because the industry has yet to standardize on any one type of low-k material, most of these issues are not yet clear (see " Removing Barriers to Low-k Dielectric Adoption "). Two big concerns are the porosity of the material, and how well a copper/low-k stack will stand up to conventional CMP.
Etch challenges
There are several ways to implement a dual-damascene process, including line first, via first and a buried etch mask/self-aligned via method. Via first is the most popular. The basic steps of a via-first process are:
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Deposition of a thick dielectric (the thickness is tailored to include both line and via dielectric), which may include a thin etch stop layer.
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Via pattern is etched through the entire dielectric stack.
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Photoresist processing for trench pattern. The buried etch stop is used to terminate the trench etch.
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Photoresist removal.
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(Source: FEI) |
In earlier generations, the via and line dielectric layers were separated by a thin intermediate layer, such as SiN or SiC, as a trench etch stop. More advanced processes omit this layer to reduce cost and improve performance. "Because there is no stopping layer, one of the biggest challenges in the via-first etch process lies in being able to prevent fence or veil formation, while still producing the desired profile with minimal faceting," said Steve Lassig, senior manager in the Process Integration Group at Lam Research (Fremont, Calif.). "For both low-k and FSG-type processes, as you're etching a trench over a via, you have to manage the top of the via. If you do this incorrectly, you can leave a veil or a fence around the via inside the trench. You can get the copper in there, but there can be problems with microvoids, increased resistance and reliability."
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1. Common problem areas in a copper via and line. (Source: FEI) |
The spin-on antireflective material applied just prior to trench lithography can leave varying amounts of polymer in the vias. This via plug is helpful in protecting the barrier during the trench etch, but variations in via dimensions and pattern density can affect plug formation. Many manufacturers get around this problem by filling the via with a material such as i-line photoresist and etching back to leave a plug before the trench lithography process. This lets them closely control via plug depth over a wider design rule space, but the process can create other problems.
"Certainly, as we go to low-k, having a plug is a little more challenging because it has to be removed at some point, just like photoresist. The strip must be aggressive enough to remove the plug and the resist, while minimizing any residue. Because the low-k materials are fragile, the strip process must also be gentle enough to prevent bowing or sidewall damage that would increase the effective k value. Although these problems can significantly impact yield and reliability, recent development results suggest there is adequate process margin to optimize for various manufacturers' requirements," Lassig added.
Diffusion barriers
After the trench and vias are formed, the diffusion barrier/liner is deposited, typically by PVD. In addition to being very good at blocking the diffusion of copper, the liner must have excellent adhesion to the dielectric and the copper. Good adhesion is necessary to resist delamination during processing or thermal stressing, and for electromigration resistance. "Electromigration and stress migration are the biggest problems in copper interconnects," said Wilbert G.M. van den Hoek, CTO and executive vice president of integration and advanced development at Novellus Systems (San Jose). "Copper migration is a surface phenomenon, not a bulk phenomenon, so that interface is critical."
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2. The copper and nitride interface can be a reliability concern. One solution is to remove the nitride and selectively replace it with a metal barrier. This could also reduce line-to-line capacitance. (Source: Applied Materials) |
The diffusion barrier must also have good step coverage to minimize cusping and potential voids (voids occur when the top of the opening gets pinched off). It must also be smooth and free of defects, both of which significantly impact the quality of the subsequent seed layer. It should be thin, yet have low resistance. "As we shrink, the real estate available for copper goes down, and the proportion of the barrier film in the via goes up," noted Nirmalya Maity, product manager for the Cu barrier/seed division at Applied Materials (Santa Clara, Calif.). "The contribution of the barrier to via resistance becomes more important. You have to get good barrier coverage on the sidewall where it's important from a reliability performance standpoint, but make it thinner at the bottom to minimize the via resistance."
TaN adheres very well to SiO2 and most low-k dielectrics. Ta adheres well to copper. For this reason, the barrier is often deposited as a bilayer, with TaN at the dielectric interface, and Ta at the copper interface. A variety of other materials have been investigated, including Ti/TiN, TaSiN and WNx. There also appears to be strong interest in alternative deposition technologies, in particular atomic layer deposition (ALD). ALD provides superior step coverage and good uniformity, and can be deposited at low temperatures. However, it is relatively slow and may only be cost-effective for very thin layers. For at least the next two technology generations, it appears as if PVD-deposited TaN/Ta will work just fine. "The industry is very reluctant to give up its learning on the copper-tantalum interface," van den Hoek said.
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3. By introducing the electroplating solution through the pad, NuTool’s technology achieves a high degree of planarity in the final film. (Source: NuTool) |
Another area receiving some attention is the barrier film, typically silicon nitride, that sits on top of the copper line and beneath the overlying dielectric (Fig. 2). "That interface between the copper and the nitride is inherently weak because you don't have a very good bond in there," said Girish Dixit, senior director of Applied's ECP Division. "It's also an easy path for the surface diffusion of copper. If you have defects on the surface of the trench, and you don't get a good adhesion between the nitride and the area, you can have a point where a failure can nucleate.
"One area where there's development ongoing is to deposit a higher-temperature melting material selectively on top of the copper trench," Dixit said. "That has two purposes. One is to act as a diffusion barrier for the copper that could diffuse out into the overlying dielectric. The other is to passivate that surface. Integration-wise, it has two benefits. One is a significant gain in electromigration resistance. The second is it will definitely give lower line-to-line capacitance, up to 20% lower."
Seed layer
The copper seed layer is the foundation for the subsequent electroplating step (during electroplating, it is this seed layer that acts as an electrode, conducting current from a cathode at the wafer edge to an anode at the center; this current causes copper ions to plate out from the copper electroplating solution). The main requirement for the copper seed layer is that it is continuous. Areas where the seed layer doesn't form are certain to create microvoids during the electroplating process. "What we have found out over the last two years is the seed is very susceptible to contamination, especially organic contamination," Dixit said. "It may leave a residue that is unable to plate. These manifest as voids going all the way through the film."
"You hear relatively little about the whole via cleaning issue, but a lot of the problems that we have with interconnect reliability start with an improper via clean," Novellus' Van den Hoek added.
It is possible to do "seed repair" to fix such holes, using an electroless deposition process. Some, however, see this as a band-aid approach. "From a first principle point of view, seed repair is reprehensible," van den Hoek said. "The solution should be putting it down properly in the first place."
The seed layer is typically deposited by PVD and, like the diffusion barrier, it appears as if that will be sufficient for awhile. "I think there's room in the PVD technology and in the barrier technology to extend PVD and eliminate the need for seed repair for at least one or two generations," van den Hoek said. Added Maity, "We believe PVD seed technologies are extendible to the 65 nm node generation and possibly beyond." However, there have been exploratory studies conducted on other approaches including seed repair and seedless plating for features beyond the 65 nm node.1
Two alternatives to PVD are ALD and electroless plating. The challenge with ALD is that it is slow and only cost-effective for very thin films. Electroplating on very thin films can be challenging, especially across large 300 mm wafers, where it is difficult to get adequate current all the way to the center of the wafer. Several techniques have been developed or are under development to address that.
Electroless plating is attractive in that it could eliminate the need for the seed layer. Results have been promising.1,2 A disadvantage of electroless plating is that it would likely require a different diffusion barrier than TaN/Ta, such as W2N. "I am 99% certain that Ta and TaN, unfortunately, are not the materials that will enable direct plating on barrier," said van den Hoek, adding, "The industry appears to be fairly reluctant to make that material change" due to electromigration and stress migration.
Bulk copper fill
The good news with electrochemical deposition is that it does not seem to be limited by line dimensions or aspect ratio: As long as the seed layer is good, it can fill the feature. The trick is to get good uniformity across the wafer, and to also wind up with a film that is relatively planar to ease the burden on the subsequent CMP process.
The ability to get good uniformity largely depends on how easy it is to get adequate current to the center of the wafer: Larger wafers and thinner seed layers exacerbate the problem. One solution is to increase the resistivity of the bath by reducing the pH, which makes electrons more likely to stay in the copper seed. It's also possible to break the anode into pieces and put different voltages on different pieces of the anode to maintain uniform current flow. Another approach, pioneered by ACM Research (Fremont, Calif.), is to plate only part of the wafer at one time (the copper is deposited in rings, from the outside of the wafer to the center). "We use a partial electroplating methodology," explained David Wang, president and CEO. "We can divide the wafer into a few different zones. In this way, we can handle a thin seed, as thin as 50 Å."
The other big concern with electroplating is the planarity of the final film. "Plating-wise, people are looking at a lot of alternatives, with an emphasis on how to produce a more planar structure," Dixit said. "There are two primary strategies to achieving that. One is chemically trying to get as planar a surface as possible. The other is to try to do something mechanically."
To achieve good planarity using chemicals, people have turned to what are loosely called "additives," organic materials known as accelerators, brighteners, levelers and suppressors. "The magic is in the additives," van den Hoek said. "If you just use a copper sulfate solution without additives, you would get horrible copper — it would be very rough and it wouldn't fill." The main challenge is to be able to monitor and replenish these additives, which are measured in the ppm and ppb range and are consumed over time, even if the bath is not in use (see "New Life for Copper Plating Baths ").
Local and global planarity over a wide range of feature sizes, 0.1 to >1000 µm, is difficult to achieve with chemistry alone: Adding a mechanical component to the deposition process may be necessary. One company taking this approach is NuTool (Milpitas, Calif.). Established in January 1999, NuTool's technology employs a rotating wafer in contact with a pad, and the electroplating solution is introduced through the pad (Fig. 3). "There are two unique advantages of NuTool's ECMD plating technology," said Homayoun Talieh, president and founder. "First, by placing the wafer in contact with the pad during the plating process, we are able to locally control where the plating occurs. The result of this contact plating technology is the plated Cu film is locally and globally planarized. Second, our ECMD technology also leads to a much smaller Cu overburden on the wafer as compared to conventional ECD. The combination of a thin overburden and a planar Cu film will significantly enhance the process margin for the subsequent Cu CMP step. With a planar Cu film to start the CMP process, our customers have found that there is a 2-4× improvement in the Cu dishing and erosion results. Moreover, with a thinner Cu film to polish, there will be a significant reduction in the cost of consumables associated with the Cu CMP process."
Defect Forensics in Electrodeposited Copper
Girish Dixit and Roman Mostovoy, Applied Materials Inc., Santa Clara, Calif.
Defects have a critical impact on the performance and reliability of today's chips. In copper wiring, defects can appear as scratches, surface roughness, corrosion stains, pits, voids or protrusions. These defects have a variety of different morphologies, chemical compositions and root causes, and may, in fact, originate in the current step or anywhere in the previous process flow steps. To optimize our Cu metalization processes with rapid root-cause analysis for defect elimination, we developed a methodical approach to defect reduction that incorporates identification, classification and analysis capabilities.
We accumulate morphological, chemical, and location (process layer or inspection step) defect data in searchable source identification and knowledge databases that enable immediate corrective action. Defect classification information comes from inspection and failure analysis tools including top-down SEM, FIB-SEM cross-sectioning and microanalysis that is collected during process development, tool engineering and qualification at Applied Materials and customer sites. Defect information is continually added to the databases, providing a comprehensive root-cause analysis methodology that is, in effect, a rapid-response "expert system."
When a defect is found, the physical appearance of the defect is the first clue to the source. Its characteristics are automatically compared using both text and image matching with source identification data and corresponding known examples. The examples are matched with data in a cause-and-effect database to determine the most likely root cause. At that point, a corrective action plan to reduce or eliminate the cause is implemented.
An example of a common defect that originates in previous process steps, but is not detectible until after plating, is the ring defect such as that shown in the Table. Once the origin is identified, the root cause can be swiftly located and a remedy implemented, saving costly loss of yield and time-to-market for new chip technologies.
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