Why 3-D TSV is Hotter Than Hot
The adoption of 3-D TSV technology promises higher clock rates, lower power dissipation, and higher integration density.
E. Jan Vardaman, President, TechSearch International Inc., Austin, Texas -- Semiconductor International, 7/11/2008
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Through-silicon via (TSV) is a technology that allows devices to be placed and wired in 3-D. The adoption of 3-D TSV technology promises higher clock rates, lower power dissipation, and higher integration density. The technology will be adopted in many applications because it solves issues related to electrical performance, memory latency, power and noise — on and off the chip. For some applications, a high-bandwidth memory interface to the logic has been the main driver for the development of the technology. Both logic and memory device applications are expected to begin in the next few years.1 The first application of the technology in production today is CMOS image sensors.
The Micron spin-off Aptina (San Jose), Oki Electric (Tokyo), STMicroelectronics (Geneva) and Toshiba (Tokyo) have announced image sensor products for camera modules. Aptina’s wafer-level camera (Fig. 1) has a Z height of only 2.5 mm, enabling the design of an ultraslim mobile phone handset. The addition of digital signal processing (DSP) to image sensors is anticipated in future camera module versions.
| Aptina’s wafer-level camera (WLC). |
TSV is a hot topic. Registration for the TSV panel discussion at SEMICON West has exceeded 1000 people. Why are so many people interested in this topic, and what does it mean for semiconductor materials and equipment companies? Depending on the size of the market and adoption rate, TSV represents an additional market for equipment and material suppliers. The TSV process includes equipment for via fabrication, via filling, diffusion barrier deposition, metallization, wafer thinning, dicing and bonding.
The primary materials routinely consumed in the TSV process application include photoresist, developers, removers, adhesion promoters, protective coatings, dielectrics, electrolytic plating chemicals, wet etch chemicals and wafer-bonding temporary adhesives.
When to form vias is an open question. The TSV can be inserted either just before device fabrication, before the front-end-of-line (FEOL), or just after the devices have been fabricated, but before the fabrication of the on-chip interconnect, before the back-end-of-line (BEOL). No single process has emerged as the most popular one, and equipment and material sets vary by company and application. For example, there is no set method to form or fill vias. While many companies use deep reactive ion etching (DRIE) to fabricate vias, some companies are also investigating the use of laser technology.
There is no question that 3-D TSV will be adopted, but the timing for mass production depends on how TSV compares in terms of cost with existing technologies. There are several challenges to the adoption of 3-D architectures. These challenges need to be overcome for the technology to see widespread adoption.
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Commercial availability of EDA tools and design methodologies
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Thermal concerns caused by the increased power densities
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Test, especially for repartitioned logic and memory
3-D integration technology will not become commercially viable without the support of EDA tools and methodologies that will allow circuit designers to use the technology.2 Design tools remain a weak link in the 3-D infrastructure, with better thermal modeling, finite element analysis, floor planning and layout tools all required for smooth 3-D design flows. Current design tools used for 2-D ICs cannot be easily extended to 3-D ICs.3 Because of this, 3-D integration has been limited to applications such as image sensors and applications within companies that structure their own design tools. Taiwan Semiconductor Manufacturing Co. Ltd.'s (TSMC, Hsinchu, Taiwan) recent announcement as part of its Open Innovation Platform and the company’s work in developing design software and introducting of a SPICE tool design kit will aid the adoption of TSV technology for customers using its foundry services.
Many companies are still investigating test issues associated with the adoption of TSV for more complicated devices in a production environment. Many researchers assume that known good die will be available, but test methods are still in development and little has been publicly disclosed. New probe technology may be required with the introduction of TSV.
While much progress has been made in thermal issues with TSV technology, additional developments will still be required.
Despite remaining issues, 3-D TSV technology is moving from R&D into production. TSV structures can be fabricated. Low-cost fine via hole formation and highly reliable via-filling technologies have been demonstrated; process equipment and materials are available, and tools and unit operations are reasonably mature.4 CMOS image sensors are in volume production with TSV. For other applications, the adoption is longer than originally imagined. More than 50 companies have 3-D TSV research projects or production plans, and the list continues to expand.
References
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E. Jan Vardaman, “The Z-Direction Goes Vertical,” Circuits Assembly, July 2008.
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P. Garrou, J. Vardaman and P. Franzon, "Through Silicon Via Technology: The Ultimate Market for 3D Interconnect," TechSearch International Inc., January 2008.
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Y. Xie, G. Loh, B. Black and K. Bernstein, “Design Space Exploration for 3D Architectures,” ACM J. on Emerg. Tech. in Comp. Systems, 2006, Vol. 2, No. 2, p. 65.
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E. Jan Vardaman, “3-D Through-Silicon Vias Become a Reality," Semiconductor International, June 2007, p. 36.
What's Delaying the Adoption of 3-D TSV?
02/09/20103-D ICs Enter Commercialization
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