Imprint Lithography Moves Closer to CMOS Requirements
Aaron Hand, Executive Editor, Electronic Media -- Semiconductor International, 2/25/2008
Molecular Imprints Inc. (MII, Austin, Texas) today introduced the Imprio 300, the latest in its family of imprint lithography tools for semiconductor applications, which brings with it a 2.5× throughput improvement over its predecessor. It also achieves significant improvements in resolution, overlay and cost of ownership (CoO), putting nanoimprint lithography further along on its CMOS roadmap.
An enhancement on the existing platform, the Imprio 300 improves on key performance areas over the 250, including a 150% boost in throughput and overlay tightening by at least 30% to sub-35 nm in mix-and-match lithography situations. “The Imprio 300 is rolling out now for continuing 22 nm process development, and development and integration for 32 nm and 28,” said Mark Melliar-Smith, CEO of MII. “We will get through a series before we hope, eventually, to get something out where we can get the performance of the tool to a point where it truly will be the manufacturing solution as you go out to 22 nm half-pitch.”
| The Imprio 300 improves throughput to 4 wph. |
The significant throughput enhancement is a move from 1.6 wph on the Imprio 250 to 4 wph on the new tool. “Not where it needs to be,” Melliar-Smith conceded, “but lots of progress, and lots of progress coming.” Every throughput improvement is an improvement in CoO, and a step closer to the 20 wph goal for high-volume manufacturing. “We believe that, once we get up to 20 wph, it becomes more of a cost of ownership issue. And we believe at 20 wph we will have the best cost of ownership of sub-30 nm lithography. So that’s our target.”
Overlay has been easier to achieve for MII in large part because the company’s S-FIL (Step and Flash Imprint Lithography) technology imprints into liquid droplets rather than a solid. This makes the tools faster and more compatible with CMOS processes because they can operate at room temperature. “Right now, I think a lot of our competitors find overlay extraordinarily difficult to do, if not impossible in the imprint space because they work essentially with materials that have to be heated up to flow,” Melliar-Smith said.
Overlay performance on the Imprio 300 has reached sub-10 nm levels in test devices. And Toshiba presented results at the IEEE Lithography Workshop in Puerto Rico in December showing that they’re now down to 20 nm feature sizes, with very good lithographic quality in terms of line edge roughness (LER) and CD uniformity. They quoted feasibility beginning to approach 10 nm on overlay.
“Some of our customers have said that, for particularly 30 nm half-pitch, they can probably get by with 15 nm overlay, mix and match,” Melliar-Smith said. “Other customers want better than that, and so 15 nm I think is probably a bare minimum, is the way I would look at it. I want to see better than that, and that’s why we’re so excited to see what Toshiba was beginning to talk about. Under the right circumstances, boy, you can do really well. Now, I’m not saying again that you would necessarily assume that everybody can do that. There’s a lot of skill involved, and credit to our friends over in Yokohama. But yes, we need to get down to an overlay which is acceptable for our customers.”
MII took several steps to make improvements to the Imprio 300, which is expected to begin shipping around the middle of this year:
-
The machine incorporates an improved overlay alignment system, including improved mag controllers, which makes the head better.
-
MII worked on the way the template interacts with the substrate and the fluid to accelerate the filling speed.
-
The dispensing system is enhanced, allowing the drops to be placed more accurately, also contributing to accelerated fill speeds.
-
The tool includes a new version of the graphical user interface, making the tool simpler for an operator to use.
-
Reliability of the tool has been generally enhanced.
The enhancements to the Imprio platform are important steps for MII’s pursuit of the CMOS market, in addition to a solid business in patterned media. “In terms of where we’re going in CMOS, we are focused on NAND,” Melliar-Smith said. “NAND is driving the roadmap, which plays to our resolution strengths. It’s also a big market, which is important for us.” He is positioning the Imprio platform as the lowest-cost tool, and a lower-risk alternative to extreme ultraviolet (EUV) lithography. “The fact that we’ve got a tool out with a CMOS customer, and have had for many months, I think is evidence of that. And certainly, one of the joys of people who use imprint lithography is DFM goes away. There’s no OPC, there’s no phase-shift mask, there’s no huge compute farms trying to do the inverse lithography. The technology is a drop-in replacement for optical lithography. You don’t have to change the process upstream or downstream.”
Based on all of these factors, Melliar-Smith said, the semiconductor industry is beginning to show increasing interest in nanoimprint lithography. With the extreme costs and complexity associated with double patterning, the industry needs a single-exposure solution, he said. “Nobody but nobody wants to have to triple the number of steps and triple the cost of their lithography. If there’s any doubt at all that people who can do one exposure rather than three prefer that approach. Now, whether that one exposure is EUV or imprint remains to be seen. But I think it’s fair to say that yes, I think people are pretty unhappy, frankly, in the industry, about the cost of lithography, both in terms of the number of steps and also in terms of the cost of the tools.”
-
One area that seems to be overlooked in imprint discussions, especially when touting a projected benefit in cost of ownership, is the cost impact of template cleaning. At the current state-of-the-art, you are looking at potential clean frequencies of more than once per lot. This means you need a backup template or smaller lot sizes. The costs associated with clean and requal add substanitally to COO. Extending clean frequencies to once every 2 lots could allow imprint to meet its promise of the most cost effective 32nm NGL.
David Jimenez - 2/26/2008 1:12:00 PM CST -
Prof. Guo and X. Cheng at University of Michigan have shown that by blocking UV light in areas where residual layers are expected to form, the residual layers can be eliminated. Microelectronic Engineering, vol. 71, p. 277.
guest - 2/26/2008 12:51:00 PM CST -
The requirement for residual layer removal is unique to nanoimprinting. Is the residual layer thickness expected to scale?
guest - 2/26/2008 5:33:00 AM CST
