TSV Apps Need TSV Tools
While key applications in CMOS image sensors and stacked memories continue to drive 3-D technology, a significant need from the tool side is still unmet: production-worthy throughputs.
Laura Peters, Editor-in-Chief -- Semiconductor International, 7/1/2008
While key applications in CMOS image sensors and stacked memories continue to drive 3-D technology, a significant need from the tool side is still unmet: production-worthy throughputs. The technologies used to create and fill through-silicon vias (TSVs) — whether it be etching, plating or chemical mechanical planarization (CMP) — need to perform at much higher rates to make 3-D technology cost-effective, according to Kyle Kirby, engineering supervisor at Micron Technology (Boise, Idaho). He spoke at Semitool’s latest Peaks Symposium on Electrochemical Processes for Microelectronics, held in Kalispell, Mont. “We need CMP slurries just for TSV,” Kirby said. “Etching the vias is a slow process and plating, too, needs to be speeded up as much as possible.”
Of course, DRAMs are an extremely cost-sensitive market, so Micron is investigating several different 3-D schemes, including via-first and via-last methods, laser drilling and reactive ion etching (RIE), as well as polysilicon or copper fills. “In what we call the via-first first approach, polysilicon vias are fabricated into the substrate before any of the device is built up,” Kirby said. “Wouldn’t it be interesting to be able to purchase substrates with TSVs all ready to go?”
Chip stacking with interconnecting TSVs is definitely in DRAM’s near future, just because the performance of even stacked memory packages is limited. Kirby mentioned that tungsten can currently fill higher-aspect-ratio vias than copper, but copper is more prevalent.
Jan Vardaman, president of TechSearch International (Austin, Texas), also presented on TSV technology and applications. “Perhaps the most controversial is NAND flash, because memory manufacturers are saying that 3-D integration at an existing node will be less expensive than going to the next node. Now, it’s important to note that not everybody agrees with that,” she added, pointing out that Intel (Santa Clara, Calif.) and Spansion (Sunnyvale, Calif.) have said they will not use TSVs in flash because they are too expensive. On the other hand, NEC Corp. (Tokyo), Oki Electric (Tokyo) and Elpida Memory (Tokyo) expect to have TSVs in commercial memory production by 2010. Samsung (Seoul, South Korea) is also aggressive with TSV technology, having announced that it is combining 2 Gb DRAMs to create a smaller, faster 4 Gb DIMM (dual inline memory module) that uses less power. Vardaman also pointed out that Tezzaron (Naperville, Ill.) and Chartered Semiconductor Manufacturing (Singapore) announced ramp of a high-speed SRAM product that is double stacked to create a 144 Mb SRAM replacement product.
Large memory capacity in a limited area
Reducing cost through conventional scaling is less effective at increasing the capacity for a given chip size, according to Vardaman. What’s needed for cost reduction is the vertical stacking of NAND flash wafers on wafers. She showed a cross-section of polysilicon TSVs interconnecting NAND chips (Figure).
| 50 µm pitch polysilicon TSVs through a 50 µm thick substrate. (Source: Mitsubishi, Workshop on VLSI Packaging, IEDM 2006) |
Field-programmable gate arrays (FPGAs) also need TSV solutions, Vardaman said. FPGAs typically have large die, so long intrachip wire lengths create delay problems. Excessive wire lengths make it difficult to increase chip-operating frequency. Also, repeaters are often used, which further increases the chip footprint. Using 3-D TSV technology, circuits are split up into smaller units and stacked for overall reduced chip area, fewer repeaters and shorter wires for less overall delay.
In the case of high-speed microprocessors, TSV use is expected to come later because new architectures must first be developed. A possible time frame, according to Vardaman, is around 2014. Despite Intel’s reluctance, it appears that TSVs will need to be adopted for microprocessors eventually because of the need to scale memory bandwidth. “The busses must become wider to deliver necessary 10-30 Gb/sec memory bandwidth, and multicore systems will require 100 Gb/sec memory bandwidth,” she said.
In addition to the tools needing to be honed specifically for TSV technology, there are design challenges, which Kirby elaborated on a bit. These have to do with real estate, routing and proximity. “You do not want your vias to be close to any other functionality, and it is desirable to have a universal pattern,” he said, adding that all die should be patterned using the same mask to reduce cost as much as possible. In processing and packaging, thermo-mechanical stresses must also be considered, both axial and circumferential.
Both speakers relayed that there will be different TSV solutions for different device technologies; no one approach will ultimately satisfy all applications.
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