Advanced DRAMs Drive High-AR Etch Advances
DRAM device manufacturers working to improve memory density and performance by shrinking design rules and die sizes face many challenges. Methods such as larger capacitor surface areas, higher dielectric constants and smaller dielectric thicknesses can extend capacitor form and function.
S. Welch, K. Keswick, P. Stout, J. Kim, W. Lee, C. Ying, K. Doan, H.S. Kim and B. Pu, Applied Materials Inc., Santa Clara, Calif. -- Semiconductor International, 2/1/2009
For years, high-aspect-ratio (HAR) structures have been a challenge to the semiconductor industry. However, what defines an HAR feature continues to evolve as the industry pushes toward higher-density devices. Almost five years ago, the most advanced HAR height:width dimensional metrics measured were ~20:1 or less for 1 GB devices.1 However, higher-AR features may be required to maintain electrical performance of future high-density devices. For example, the International Technology Roadmap for Semiconductors (ITRS) predicts that DRAM manufacturers will use capacitor ARs of ~50:1 for the 4–8 GB, 3X nm DRAM half-pitch nodes even though capacitor dielectric constants are also increasing (Fig. 1).2Figure 2 shows a SEM cross-section of a 30:1 HAR dense stacked capacitor structure etched into bulk oxide for current DRAM processes and a respective schematic of the film stack.
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| 1. ITRS DRAM stacked capacitor technology requirements for structure aspect ratio and dielectric. (Source: ITRS)2 |
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| 2. Cross-section SEM image of 30:1 HAR capacitor post etch and pattern ash (a). Schematic cross-section of HAR container or contact/via1 structure (b). |
Capacitors and contacts with ARs in excess of 40:1 and higher pattern densities pose unique challenges for controlling dielectric etch processes. Current HAR capacitor, contact and via structures are generally small round or oval features formed in thick oxide dielectric films.3 Development of high-yield HAR etch processes requires in-depth understanding of critical on-wafer requirements and the influence of process parameters and etch reactor design interactions on device performance. The ability to manipulate and control key elements of capacitor formation enables yield and productivity benefits for the development of production-worthy HAR processes at 45 nm and beyond.
HAR DRAM devices
DRAM devices leverage cylindrical capacitors as the memory storage element. To increase capacitor storage performance and mitigate electron leakage, multiple approaches have been explored. Since capacitance is a function of the capacitor's area and dielectric constant, and inversely related to dielectric thickness, any increases to the capacitor's area or dielectric constant, or reduction of dielectric thickness, will improve electron storage performance. Thus, one approach is to build cylindrical capacitors at higher ARs. HAR features will allow the effective area to increase, but challenges remain to ensuring that these structures are created free of defects. Higher-k dielectrics may mitigate the requirement for extremely high ARs if they prove production-worthy.4
In a DRAM device, contacts and vias are designed to provide maximum electrical conductance between the transistor's active areas and back-end wiring. Depending on the device stack design and capacitor height, these electrical contacts must pass through thick dielectric layers to connect with the transistor. The AR also depends on whether the contact is located in dense or isolated regions, and the height of the overall transistor element. Dense regions generally have higher ARs because of tighter CD requirements. These features' AR is directly influenced by innovations in capacitor development.
A diagram of a typical HAR film stack cross-section schematic detailing the film materials is shown in Figure 2b. The film stack includes a patterning layer, oxide as the dielectric bulk, a silicon nitride barrier (etch stop layer) and the conductive underlayer. Historically, the patterning material has been photoresist (PR), but more recently amorphous carbon or spin-on hardmask materials have been added for increased layer etch selectivity.5 In some cases, an additional layer is integrated into the capacitor's film stack that prevents structures from toppling once the bulk oxide layer is removed in a subsequent process step. Current device feature sizes, or critical dimensions (CDs), are 50–100 nm and dielectric film thicknesses are 1.5–2.5 μm.2 Because manufacturers' processes vary, this discussion focuses primarily on the film stack described in Figure 2b.
Etch process
The HAR etch process consists of multiple etch steps that are tailored to meet critical profile, CD, selectivity, uniformity and repeatability requirements. The completed etch must provide features that support capacitor formation or provide electrical contacts. The unit etch process includes five primary steps:
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BARC/DARC etch with C-F plasma chemistries to define CDs.
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Hardmask etch and PR strip to open the hardmask patterning layer and completely remove PR and BARC layers.
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Dielectric etch with C-F chemistry to form the HAR structure and make contact with the etch stop.
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Etch stop removal with C-F chemistries to access the underlayer.
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Patterning layer removal with O2 ash.
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The demands of creating production-worthy HAR features require that a defect-free, repeatable etch be conducted. Multiple defects can arise from HAR etch processes that need to be considered when optimizing the etch process (Fig. 3). In addition to the structural requirements, efficient, reproducible production process control is essential.
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| 3. Example HAR etch defects: Bowing (a), variations to top and bottom CD (b), necking (c), bending (d) and pattern distortion (e). |
HAR CD and profile control
Top and bottom CD management are integral to achieving good electrical performance. If the top CD is too big or the perimeter is roughened, then feature-to-feature isolation is jeopardized; when capacitors or contacts are formed they can bridge together and short circuit, resulting in yield loss. Top CD control is achieved by balancing reaction chemistries to fine-tune selectivity during BARC/DARC open etch and high mask selectivity during oxide etch.
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| 4. With different combinations of bias frequencies, ionization energies can be optimized to control etch performance. |
The bottom CD directly influences electrical contact. If the bottom pattern is too small, contact resistance will be very high and large leakage currents may occur. An example of an HAR structure with poor top and bottom CDs is shown in Figure 3b. Bottom CD control is achieved with high ion energy and optimized ion energy distribution. With optimal ion energies, reactive species/polymer creation is controlled and hence etching of the structure can be managed. High-power capabilities can help improve reactive species availability deep in the structure. One way to attain layer-appropriate plasma densities and ion energies is to use a combination of RF frequencies within the reactor. Figure 4 demonstrates how various combinations of bias power frequencies result in different distributions of ion energy.
This range of distributions provides flexibility to select appropriate power parameters that allow for optimal creation of reactive species at appropriate concentrations. Furthermore, this tuning can allow for better handling of high DC voltages without arcing and of thermal loads for more stable and repeatable temperature management. As transistors shrink, allowable CD specification ranges, such as the top-bottom CD (TBCD) ratio, are also tightening. Experimental results leveraging a dual RF frequency approach have demonstrated TBCD ratios in excess of 80%. Figure 2a demonstrates a good TBCD ratio in excess of 90%.
Mask and stop layer selectivity are key considerations in developing HAR contact etch processes. Mask selectivity affects top CD control and striation performance. Stop layer selectivity is important to mitigate etch depth and microloading non-uniformities. If stop layer selectivity is not achieved at the bottom of the features, excessive etching of the etch stop or underlying layers results in electrical opens or shorts, high leakage and yield loss. To maximize etch selectivity, a combination of chemistry and reactor parameters are employed. The choice of chemistry is determined by the layer being etched. RF frequencies, powers and pressures are optimized with chemistry to meet selectivity requirements while maintaining profile and etch depth capability. A mixture of high and low RF frequencies is optimum for achieving selectivity to the mask and underlayer due to the ability to optimize reaction parameters.
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| 5. General mechanisms influencing bowing (a), and improvements to bowing with dual-frequency process control (b). |
Bowing, necking and pattern distortions are issues related to profile control. Bowing results when anisotropic etch of the HAR feature's walls occurs.6 Bowing is believed to happen because of the inherent likelihood of charged species in the plasma having an angular incidence. This phenomenon can be intensified by other mechanisms that cause ionized species' paths to travel non-normal to the wafer plane, such as sidewall deflection and charging. A bowed structure is shown in Figure 3a and a schematic of bowing mechanisms in Figure 5a. Bowing is most problematic in dense patterns, where the risk of neighboring features electrically shorting from the significant narrowing of the inter-dielectric barrier is higher. Multiple methods have been identified to increase the ionized species' probability of traveling in wafer normal paths, including optimization of ionization energy and plasma density with flexible source/bias power and gas control, reducing electrical charge buildup and increasing protective passivation of the sidewall with gas selection and control, and reducing neck formation by managing organic polymerization in the plasma and adsorption onto the sidewall. For example, by leveraging novel approaches for dual-frequency bias tuning, a wider range of optimal process parameters exist, such that advanced HAR etch sidewall profiles can be demonstrated (Fig. 5b).
It is possible for polymers from organic plasma etchant species to form and adsorb onto the HAR sidewall, near the top of the features, as the etch proceeds creating a "neck" (Fig. 3c). Although most of the necking is removed when the patterned layer is ashed, it is still critical to control the extent of polymerization and necking. Too much polymer necking can create tapered profiles with out-of-spec top and bottom CD values, and at an extreme can lead to the creation of a complete etch stop that prevents the full etch of the HAR structure. Insufficient polymer creation can have negative effects as well because sidewall passivation can be limited, resulting in added bowing. Furthermore, asymmetric necking can cause ionized species to bend or deflect, leading to bowing or structural deformations. To minimize necking buildup, process engineers must optimize plasma reaction chemistries for the patterning and oxide etch steps, including gas flows, concentrations and pressures, as well as tune plasma power and chamber temperature to control the creation of organic polymer.
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| 6. Modeling helps improve understanding HAR etch characteristics. Bending patterns observed in HAR etch cross-sections (a) are mimicked by modeling non-uniform field effects’ influence on off-normal ion incidence (b). |
When etching HAR features, some profiles become "off-normal" or twist and tilt as the depth increases (Fig. 3d). In some instances, the twist or tilt does not begin until after some critical depth (i.e., it is AR-dependent). Also, the top-down pattern can be distorted between feature top and bottom. For instance, a circular opening can become oval or bean-shaped (Fig. 3e). These distortions can impact electrical performance or limit feature density. These types of distortions imply that forces such as local etch environments with deflected or non-normal incidence of reactive ion species or extreme wafer edge effects are asymmetrically influencing the reactive species' path as the etch proceeds. By leveraging proprietary modeling capabilities, twisting has been shown to be influenced by asymmetric incident of ions or polymer deposit. Figure 6b shows the result of two slices of a modeled 2×1 via structure exploring off-normal ion incidence due to field bending near the sheath. The tilt of the feature reflects the off-normal ion path and matches well with experimental results (Fig. 6a). Hence, proper control of polymer creation and chamber electric fields can help to mitigate distortion issues.
Production considerations
Uniformity refers to structure variability, from feature to feature across the wafer, that must remain within tolerable ranges. Furthermore, uniformity issues that arise from dense/sparse areas or at the extreme edge of the wafer create additional challenges.7 If pattern uniformity cannot be controlled within SPC limits, there is a higher risk to electrical performance and wafer yield.7 The most effective means of controlling pattern uniformity is to ensure that the plasma density remains consistent across the wafer and at each localized feature surface, such that similar concentration levels of reactive species are available for etching. By tuning bias power, gas parameters (including neutral species management), and chamber and wafer zone temperatures, more uniform plasma densities and reactions can be achieved.
Managing the etch rate of HAR features can be a challenge because etch rates will typically decrease as the etch depth and aspect ratios increase during the process.8 Multiple mechanisms have been identified that contribute to this effect, including neutral and ion species interaction and charging.8 Furthermore, features in dense pattern regions can etch at different rates than those in sparse regions, a phenomenon known as microloading.8 Balancing these multiple considerations while maintaining control and availability of reactive species in the local etch environments, as well as proper removal of reactive products, is crucial. Proper selection of bias power, system temperature, chemical species, and gas pressures/flow will directly influence reactive species and byproduct concentrations and therefore etch rates. For example, by implementing dual-zone wafer temperature control, etch rate nonuniformity across the wafer can be reduced by up to 75%. By managing the etch rate of the different AR features, under or over etching can be prevented and, more importantly, overall etch time can be optimized.
The ultimate objective for manufacturers is to repeatedly run very high volumes of wafers through multiple chambers and tools, with minimal variation wafer to wafer, lot to lot, and chamber to chamber. The key is control over process conditions, and minimizing hardware variation and instability, while providing for a wider process window with controlled CD, profile and etch rate variations. By reducing the probability of variation, uniform die-to-die performance can be better guaranteed. The main method for achieving process repeatability is to ensure that each wafer encounters the same process chamber conditions. One method for ensuring a similar chamber environment for each wafer is by conducting an in-situ chamber clean operation after each wafer process. By leveraging very high frequencies, efficient cleaning that extends the time between wet cleans, lower voltages that reduce chamber erosion rates, stable etch performance and low defectivity can be realized. However, process and chamber cleaning alone cannot provide the solid foundation for robust repeatable manufacturing. Robust reactor and hardware design and tight controls around all critical system components are also essential.
HAR features will continue to drive dielectric etch technologies in the foreseeable future. Etching these features requires process knowledge as well as physical and chemical control of the etch environment. A delicate balance is always at play to optimize HAR etch characteristics free of defects. Although advancements in high-k dielectrics for capacitor creation could help mitigate the progression to extremely high ARs, changes in materials and feature densities will continue to test etch performance.
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Good job! It's nice to see a concise review of all the HAR "headaches" in dielectric etch... brings back some memories. Hope all is well in B81.
Steve Shannon - 4/14/2009 1:53:00 PM CDT -
Badly written introduction.
The introduction to this article has two sentences: "DRAM device manufacturers working to improve memory density and performance by shrinking design rules and die sizes face many challenges. Methods such as larger capacitor surface areas, higher dielectric constants and smaller dielectric thicknesses can extend capacitor form and function."
These two sentences are completely disconnected. What do the methods mentioned in the second sentence have anything to do with challenges faced by DRAM manufacturers mentioned in the first sentence?
Was this introduction written by a robot? You should fire the editor in charge of articles on this site.
O - 3/2/2009 7:24:00 PM CST
