PECVD Could Take Low-k to 2.1
Laura Peters, Lead Technical Editor -- Semiconductor International, 10/19/2007
So far, the industry sees a clear path to integrating k=2.3 materials into multilevel metallization scheme using plasma-enhanced chemical vapor deposition (PECVD) dielectrics. This represents something of a breakthrough because, at one time, k=2.5 was looking like the lowest value that could be achieved and successfully integrated with the needed hardness, modulus and other properties necessary. However, with such aids as low-damage etching, metal hard masks, and ashing with reduced and remote plasmas, IC manufacturers and the supplier community have worked together to successfully scale k values down to around 2.3. At the recent IMEC Annual Research Review Meeting this week, Rudi Cartuyvels, department director of interconnect technology and technology options at IMEC (Leuven, Belgium), explained that the research center and its partners are currently integrating k=2.3 materials into production processes. He gave an update of interconnect activities at the research center and pointed out some of the hot-button issues:
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Scaling of k to 2.1 with PECVD seems likely
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Air gaps have potential for k&2.0
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Because of the sensitivity of porous low-k dielectrics to plasma damage, all-wet strip processes are badly needed
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When ionized physical vapor deposition (iPVD) of copper reaches scaling limits, alternatives are needed
The main causes of damage to low-k dielectrics include strip damage to the exposed top surface, the copper oxide reduction plasma step, and the reactive pre-clean step. Dielectric chemical mechanical planarization (CMP) and wet strip can also cause some damage. As companies have moved from the denser silicon oxycarbide-based dielectrics (k~2.7, SiCOH) to more porous version (pore size ~2 nm), plasma damage has been kept under control by using polymerizing, oxygen-free etch processes where the polymer shields the influence of the plasma. Also, many companies are using metal hard masks, performing the photoresist strip after the MHM open and before the low-k etch. In the post-etch residue removal step, extremely selective chemistries are needed to fully remove residues without depleting the low-k and affecting critical dimensions.
| All-wet selective chemistry is needed to remove the hardened photoresist crust and bulk photoresist without degrading the delicate low-k feature below. (Source: IMEC) |
Organic solvents can be used to remove the bulk photoresist, but the cross-linked photoresist crust on top of the feature requires some other approach (Figure). “A combination of mechanical and chemical force is needed to get rid of this crust,” Cartuyvels said. Also, for environmental reasons, companies would like to get away from the organic solvents and use just one wet chemical to remove all the resist. When asked about the likelihood that the industry will use low-k pore sealing methods, Cartuyvels said that if the pore sealing method is plasma-based, he does not think it will be used.
The air gap process that IMEC is investigating consists of a stack of porogen/porous hard mask (oxide-like)/resist that is patterned, hard mask opened, etched and stripped. This is followed by barrier/seed metallization and copper CMP. Then a porogen decomposition step is performed using ultraviolet (UV) radiation to create the air gap where the porogen material resided. This single litho step process is simpler than other approaches that have been proposed in the literature.
Once interconnect trenches scale below around 40 nm, iPVD seed coverage at the feature bottom becomes marginal and pinch-off at the feature top becomes a big problem. IMEC is investigating self-assembled monolayer barriers that would deposit on the sidewalls of trench features, while a sacrificial barrier is deposited and removed from the feature bottom. Still in the early stages of development, these self-assembly processes use commercially available molecules.
The other approach being evaluated involves direct plating of copper on ruthenium. The key challenge is making the appropriate changes to the plating bath to achieve uniform copper film growth.
IMEC-ASML Present 193 nm Results
02/09/2010
