Heterogeneous Channels: A Goal of EC’s 'Duallogic' Project
Staff -- Semiconductor International, 2/11/2008
A European project to create dual-channel CMOS was announced today, with the goal of combining germanium PMOS and III-V NMOS channels for post-22 nm CMOS.
The “Duallogic” project will have a total budget of €9.1M ($13.2M) over the three-year term, with €5.8M ($8.4M) coming from the European Commission’s 7th Framework Program (FP7) in Information and Communication Technologies. The project will include European IC and equipment manufacturers, technology development laboratories, research centers and universities, including Aixtron (Aachen, Germany), CEA-LETI (Grenoble, France), IBM-Zurich, IMEC (Leuven, Belgium), Katholieke University (Leuven), National Center for Scientific Research Demokritos (Athens), NXP Semiconductors Inc. (Eindhoven, Netherlands), STMicroelectronics (Geneva), and the University of Glasgow.
Duallogic project leader, Athanasios Dimoulas of the National Center for Scientific Research Demokritos, said that high-k dielectrics and metal gate electrodes came in at the 45 nm node. The next step may be new materials in the active channel regions. “If the heart of the transistor, which is the gate dielectric, could be changed, eventually any other part of the transistor can be changed too,” he said.
The Duallogic project has three main project components aimed at creating germanium PMOS and III-V NMOS channels on a silicon substrate. For a larger version of this chart,  .
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Charge carriers in germanium have higher mobility, but Dimoulas said that “after five years of intensive research, it turns out that germanium only outperforms silicon for PMOS and, therefore, a complementary MOS technology made entirely of germanium does not seem to be feasible at present.”
On the other hand, III-V compounds such as GaAs or InGaAs are effective for NMOS, but they seem to be unsuitable for PMOS. “Contrary to the common belief a few years ago, germanium and III-V compound semiconductors are not competitors; instead, they are materials which could complement each other on the same chip,” he said.
The goal of the Duallogic program will be the co-integration of germanium PMOS and III-V NMOS “side-by-side on a silicon substrate to demonstrate for the first time a dual-channel CMOS technology.”
The project will seek to create a “scalable and manufacturable” process, employing a silicon-compatible process in a 65 nm technology on a 200 mm pilot line. “We expect that Duallogic will determine by the end of 2009 whether the approach is a viable option for CMOS beyond 22 nm,” he said.
Sematech (Austin, Texas) also is studying heterogeneous CMOS as part of its front-end transistor program.
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