CoO Dictates Memory's Move to Copper
Tom Caulfield, Executive Vice President, Sales, Marketing and Customer Service, Novellus Systems Inc., San Jose, www.novellus.com -- Semiconductor International, 12/1/2008
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Ten years after its initial introduction for logic device manufacturing, copper interconnect technology is rapidly being adopted for memory chip production. For advanced nodes, the technical advantages of a copper metallization scheme over an aluminum interconnect have long been recognized.
In comparison to aluminum interconnects, the reduced RC delay of copper means increased device speeds, lower power consumption, and lower operating temperatures — features that are important for all semiconductor applications. For memory chipmakers in particular, copper allows longer wiring runs than aluminum, while supporting new DRAM architectures such as DDR3 and DDR4.
The primary driver for the migration of copper metallization into memory devices is not a technical one — it's all about cost. Recent macroeconomic issues have put unprecedented pressures on the average selling price of memory chips, requiring chipmakers to significantly accelerate cost reduction to maintain profitability. With-out question, the most effective way to reduce manufacturing cost is to leverage Moore's Law and take advantage of die shrinks associated with technology node advancements. A decade ago, in seeking to build smaller and more powerful chips, the logic manufacturers had to shift to copper interconnect for functional performance and device speed. Along the way, they discovered that copper interconnect was also a lower-cost alternative to aluminum interconnect, a lesson that has not been lost on memory chip manufacturers.
Building memory chips with copper wiring instead of aluminum is more cost-effective for two fundamental reasons. First, copper manufacturing toolsets are more productive than their aluminum counterparts. For example, in the case of the metallization process, advanced memory chips at the 3X technology node have some very aggressive metal features that are less than half the pitch and width found in 45 nm logic chips. This poses challenges that are both technical and, for high-volume manufacturing, costly.
The ability of traditional aluminum physical vapor deposition (PVD) processes to work in these extremely narrow and deep structures is highly questionable. The alternative process, chemical vapor deposition (CVD) aluminum, offers considerably lower throughputs than the PVD process, and requires expensive precursor gases. In contrast, the electrochemical deposition (ECD) metallization process used for copper is highly productive, even at advanced technology nodes where state-of-the-art ECD systems can fill 22 nm features with throughputs of >80 wph.
From the perspective of dielectrics deposition, aluminum memory devices require gap fill films that are deposited on systems with comparatively low levels of throughput. In contrast, memory chips made of copper use planar plasma-enhanced CVD (PECVD) dielectrics, and the advanced equipment used to deposit these films is extremely productive — in some cases capable of throughputs in excess of 200 wph.
So improved toolset productivity is the first reason memory manufacturing with copper interconnect has a lower cost than with aluminum.
The second reason goes to a discussion on device reliability and manufacturing yields — factors that are of significant concern to the cost-sensitive memory chip-maker. Device reliability of the memory bit line is significantly improved with copper vias compared with high-temperature aluminum plugs. Further, in terms of manufacturing yield, the planar dielectrics used in manufacturing copper memory devices are easier to pattern and etch with low defectivity in comparison with the aluminum conductive lines found in traditional memory chips. Finally, the CMP process used in copper damascene manufacturing planarizes the surface of the wafer after each deposition step, making it easier to pattern the subsequent layer. Given the challenges of an advanced aluminum interconnect scheme, a copper interconnect scheme provides inherently higher yield for advanced memory structures.
Copper damascene manufacturing for logic devices is nearing maturity, and has proven to be a relatively risk-free replacement for the subtractive aluminum metallization scheme. The primary technologies for copper metallization — copper electroplating, PVD barrier/seed and dielectrics deposition — have demonstrated remarkable extendibility across technology generations, mitigating the need for cost-sensitive memory chipmakers to replace toolsets every couple of years. The shift to copper in memory is all about reducing manufacturing process cost. The successful equipment companies will be those that address their customers' No. 1 priority — cost.
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