How Optical Lithography Prints a 32 nm Node 6T-SRAM Cell
Geert Vandenberghe, Manager, Optical Extensions and Imaging Group, IMEC, Leuven, Belgium -- Semiconductor International, 6/1/2005
The ITRS target for a 45 nm node 6T-SRAM cell requires at least a 150 nm contacted pitch when assuming a "thin-cell" layout. To achieve such a small pitch on a 0.75 numerical aperture (NA) 193 nm lithography tool, an optical k1 as low as 0.29 is needed. The traditional SRAM cell layout is, however, difficult to scale to lower k1 values. A solution is to first modify its design toward a more litho-friendly one (i.e., a unidirectional design for active and poly gates). This implies more aggressive pitches on the contact layer as well. Hence, a double-patterning approach for the contact layer, which splits the pattern into two less dense patterns, seems obvious.
In the next step, for each critical layer, the litho-friendly cell layout is further optimized by exploring different reticle (phase-shift mask) technologies and illumination possibilities (quasar or dipole), combined with state-of-the-art optical proximity correction (OPC). All these advanced lithographic techniques and good cooperation between litho and processing experts recently led to the fabrication of a fully functional 45 nm node SRAM cell implementing multiple-gate FETs (MuGFETs). Good profile and acceptable CD control was achieved for fin and gate layer. The 0.314 µm2 SRAM cell (Figure ) achieved excellent static-noise margin and showed good functionality down to 0.4 V.
What's more, the cell shows great potential for scaling toward the 32 nm node, which requires active fin pitches as low as 110 nm. A few advancements have already been implemented to further decrease the cell size: replacement of the polysilicon gate electrode by a metal gate stack and the use of very aggressive OPC. The resulting SRAM cell yields a very good prospective: A fin pitch of 144 nm and an optical k1 of 0.27 was achieved with dry 0.75 NA 193 nm lithography. The litho-friendly design concept, the optimized optical extensions, including the very aggressive OPC, and resist choice are key issues to obtaining this very low k1 value. In the future, using hyper-NA immersion lithography with an assumed NA of 1.3 will allow scaling of the SRAM cell to 32 nm node dimensions. In other words, optical lithography will allow printing the fins and gates of a 32 nm node 6T-SRAM cell.
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| Tilted SEM view of an SRAM cell using MuGFET devices after poly patterning. (Source: IMEC) |
But there are a few critical issues that deserve particular attention. A first important roadblock is related to the imaging of the contact hole layer and overlay control of two contact prints. To relax the pitches on the contact layer of the 45 nm node cell, a double patterning approach was used. But after the split for a 32 nm node contact layer, the minimal pitch remains very aggressive. The use of a 6% attenuated phase-shift mask (attPSM), in combination with aggressive off-axis illumination and the placement of sub-resolution assist features, cannot guarantee sufficient process yield. In addition, at some places, the space between the contacts becomes very small. Hence, the overlay of the two contact prints will be very critical to avoid shorts. In conclusion, by making the active and poly layer litho-friendly and printable with ArF immersion lithography, printing the contact layer becomes a major hurdle and may require a redesign as well.
A second critical issue is line edge roughness (LER), which in general is one of the most worrisome issues faced by next-generation lithography. Up until now, LER was only a small part of the linewidth variation budget. But because LER does not automatically scale with the improved litho conditions, it will become one of the main contributors. Optimizing LER will require, among other modifications, optimized resist chemistry.
Finally, the lithographic conditions, now optimized for printing the critical layers in memory devices, should also be compatible with logic circuits. To give an example, the optimal choice of dipole illumination of the active fin layer necessitates a unidirectional layout at the active fin layer level for the logic circuits as well. This has major implications on the layout and wiring of these circuits. Design trade-offs may be necessary to combine logic and the dense SRAMs in a design.
| Acknowledgements | ||
| The author would like to thank Serge Biesemans, Axel Nackaerts and Staf Verhaegen for the 45 nm node SRAM cell patterning work and their valuable discussions. | ||
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