IMEC Views 3-D Stacking as System Design
IMEC managers said the research center has made significant progress creating test 3-D ICs, using die-to-die stacking. IMEC's Eric Beyne said achieving coplanar and particle-free surfaces still presents processing challenges. He described the dual-damascene via processing as comparable to traditional front-end interconnect via processing, but with larger features.
Laura Peters, Editor-in-Chief -- Semiconductor International, 10/14/2008
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IMEC (Leuven, Belgium) said it has made significant progress with its 3-D SIC (3-D stacked IC) technology, including demonstration of functional 3-D ICs obtained by die-to-die stacking using 5 µm copper through-silicon vias (TSVs).
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| IMEC’s 3-D stacked IC requires die-to-die stacking using 5 µm copper through-silicon vias (TSVs). |
The research center will now further develop 3-D SIC chips on 200 and 300 mm wafers, integrating test circuits from its active partners in the 3-D integration research program. These partners include Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), Amkor, EV Group, NEXX, Applied Materials, Disco, ICOS, Qualcomm, STMicroelectronics, Intel, Panasonic, Infineon, Micron, Samsung and Qimonda, among others.
Eric Beyne, IMEC scientific director for 3-D technologies, said the cost of 3-D approaches is dominated by the capital equipment cost, with silicon etching, copper filling and die-to-wafer bonding being the dominant areas where cost/productivity improvements are needed. One difficult processing challenge for 3-D ICs is achieving coplanar and particle-free surfaces. Beyne said new cleaning steps must be developed for this application.
IMEC’s initial results are encouraging. Using its 200 mm platform, the top wafer is thinned to 25 µm, mounted to a temporary carrier, then bonded to the landing die by copper-copper thermocompression. IMEC is scaling the process for die-to-wafer bonding, and is on track for migration to its 300 mm platform. Beyne described the dual-damascene via processing as comparable to traditional front-end interconnect via processing, but with larger features and pitches, and a higher aspect ratio.
To evaluate the impact of the 3-D SIC flow on the characteristics of the stacked layers, both the top and landing wafers contained CMOS circuits. Extensive tests confirmed that the performance of the circuits does not degrade by adding copper TSVs and stacking. Ring oscillators with varying configurations were used to test the integrity and performance of the 3-D stack, distributed over the two chip layers and connected with the copper TSVs. Tested after the TSV and stacking process, these circuits demonstrated excellent integrity.
“With these tests, we have demonstrated that our technology allows designing and fabricating fully functional 3-D SIC chips. We are now ready to accept reference test circuits from our industry partners,” Beyne said. “This will enable the industry to gain early insight and experience with 3-D SIC design, using their own designs.”
IMEC is working with the International Technology Roadmap for Semiconductors (ITRS) and the Jisso packaging standards group on standards for 3-D classification based on the electronics supply chain. Beyne said the industry is debating terminology and which entity — fab/foundry, chip packaging or board assembly — will perform the interconnection steps in 3-D integration. IMEC proposes using 3-D system-in-package (SiP) to denote the most traditional 3-D packaging of wire bond to the die stack (second and third level for Jisso), whereas 3-D wafer-level packaging refers to 3-D interconnect processing after IC passivation (first level for Jisso). 3-D IC or 3-D SIC would indicate the tightest integration level, in which interconnection between chips occurs at the global or intermediate level of device wiring, defined as level 0, according to Jisso.
To address 3-D design issues at the system level, IMEC is designing a physical- and technology-aware architecture to realize the design implications early — in time to make critical decisions regarding process technology and system architecture relative to 3-D implementation. It is using PathFinding, a virtual design flow, to help identify the technology/design “sweet spot.” In the optimization, test structures evaluate TSV alignment, electromigration and yield, impact of TSVs on the back-end-of-line (BEOL) and front-end-of-line (FEOL) process, and TSV effect on RF test. In the initial case study of 3-D stacked DRAM, questions to be answered at the system design level included how many I/Os proved optimal and whether memory architecture changes were necessary. At the physical design level, questions included how to layout and power through the TSVs, and whether the TSVs caused heat distribution issues. At each step in the modeling process, cost, performance and power were estimated, then validated in silicon.
IMEC will hold a 3-D workshop Nov. 14 in Hsinchu, Taiwan, to allow open discussion among key parties in the supply chain of the many unresolved issues in 3-D design and manufacturing.
