IMAPS Panelists Address Tough 3-D Challenges
A panel of experts at the IMAPS Device Packaging Conference considered the challenges facing 3-D manufacturing. Panelists considered the role of foundries, assembly and test vendors, EDA tool providers, and equipment companies, while answering seven key questions posed by the moderator.
Philip Garrou, Microelectronics Consultants of North Carolina, Research Triangle Park, N.C. -- Semiconductor International, 3/19/2009
A panel of experts addressed the tough challenges facing 3-D interconnect commercialization at the International Microelectronics and Packaging Society (IMAPS) Device Packaging Conference in Scottsdale, Ariz.. The conference drew a larger-than-expected crowd of 510 attendees last week, prompting IMAPS Executive Director Mike O’Donoghue to say that the show “has continued to grow beyond our wildest expectations, especially in these dire economic times.”
The panelists included Bob Patti, CTO of specialty memory supplier Tezzaron Semiconductor Inc. (Naperville, Ill.); Eric Beyne, director of advanced packaging technologies at IMEC (Leuven, Belgium); Jan Vardaman, president of TechSearch International (Austin, Texas); C.J. Berry, vice president of packaging development at Amkor Technology (Chandler, Ariz.); and Bioh Kim, director of business development for the EV Group (EVG, St. Florian, Austria). Phil Garrou, principal consultant of Microelectronic Consultants of North Carolina (Research Triangle Park, N.C.), served as the moderator.
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| IMAPS 3-D panelists included (left to right) Jan Vardaman, TechSearch International; moderator Phil Garrou, Microelectronic Consultants of NC; Eric Beyne, IMEC; and Bob Patti, Tezzaron Semiconductor. |
The panelists answered a series of questions regarding 3-D IC development, starting with a stage-setting query on whether the three short-term product drivers are likely to be CMOS image sensors (CIS), memory-on-logic, and then memory stacks, with DRAM coming in much earlier than flash.
Vardaman said she believes DRAM will adopt 3-D technology before flash, noting, “Solid-state drive manufacturers don’t have it on their roadmap yet, so we know it’s further out there.”
Garrou added that consumers can buy 512 Gb solid-state drives (SSDs) today that do not contain through-silicon vias (TSVs). “When TSVs allow a reduction in cost, then the technology will become mainstream for SSDs and other flash applications,” he said.
Amkor’s Berry said TSV technology is about evolutionary steps, and “will require a mature supply chain to bring it to market for any of these applications. We’re talking about taking something from first demonstration to high-volume production, so seeing the same applications for a few years shouldn’t shock anybody…these things take time.” Beyne added that in Europe, 3-D IC processes “are beginning to show up in MEMS and automotive applications.”
Another question related to the timetable for TSV technology, which is being commercially adopted in CIS and chip-on-chip (CoC) memory-on-logic in the 2008-2009 timeframe. This will be followed by CIS backside illumination (BSI) solutions starting later this year, DRAM stacking in 2010-2011, higher-density memory-on-logic around 2012 and finally heterogeneous integration and repartitioning by 2014.
IBM getting ready for 3-D
David Danovitch, a senior engineer at IBM’s Bromont, Canada, facility, said IBM forsees using 3-D IC technology in the future. He added that there were no qualified 200 or 300 mm IBM lines running at this time capable of foundry-based 3-D integration production.
Suresh Golwalkar, principal engineer of materials at Intel Corp., indicated that Intel was examining 3-D IC technology in great depth, but that he could not share with the audience at what point Intel intends to insert such technology into mainstream products.
Beyne said simpler versions of heterogeneous integration, such as RF solutions, are being developed now, adding that they will provide an advantage to “fab lite” manufacturers. Berry added, “I wouldn’t be surprised to see a simplified version of heterogeneous integration show up by 2012 or 2013. I can envision logic deconstructed on an interposer, for example.”
Garrou argued that heterogeneous integration and repartitioning would be a boon for future fab-lite companies, since they can have the individual layers built at different foundries so they never lose control of their IP. Patti indicated that Tezzaron is indeed doing that now.
TSVs for phase-change memories
Patti predicted that in the memory field TSVs will be used first in DRAMs, adding, “Flash will come after DRAM, but phase-change memory will be before flash.”
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| Samsung’s 8 Gb DDR3 DRAM has a 1600 Mb/sec data rate. |
A third question revolved around the 3-D roadmap for Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan). In the fall of 2008, TSMC proposed a TSV roadmap for its foundries that included backside CIS TSVs at a 140 µm pitch in 2008, dropping to a 60 µm pitch in 2010, with a true via-first (iTSV) foundry flow with a 17 µm pitch coming in 2011.
The consensus among the panel was that TSMC will likely push out its planned iTSV production capability. “I have good reason to believe it’s likely to move because they’re demand-driven,” Patti said. “There would have to be strong customer demand. There aren’t enough customers demanding it right now, so I think they will push it out.” Berry concurred, saying, “Profoundly new technology such as this presents a difficult business model. It is probably is in their best interest to be conservative.”
A fourth question posed to the panel asked whether they agreed with the proposition that CIS backside vias will continue to be done at the outsourced semiconductor assembly and test (OSATS) vendors, but that in general TSVs will be a fab/foundry business.
There was complete agreement on that from the panel, but a lively discussion ensued on which companies would take ownership of the post-fab processes. Patti, Beyne and Berry agreed that it will be important that all the post-fab processes, including wafer thinning, backside processing, stacking and bonding, all be done in one place. Berry added that “foundries got burned in the bumping business” and that he sees these middle-end processes being done by the OSATS providers.
Wafer thinning ready
Asked if OSATS vendors will be comfortable thinning down to the expected ~20 µm thicknesses, Berry said, “Yes, thinning to 25 µm has been demonstrated already.” EV Group’s Kim, who has experience participating in the EMC-3D consortium, said, “Shipping thinned wafers between locations, even on a temporary handle substrate, is a concern. I’m not sure where it will be done, but I agree multiple processes done on thinned wafers should be done at one location.”
A question posed to the panelists concerned whether the required TSV equipment sets are ready for production. The panel agreed that with a few modifications the equipment is ready, and Kim added emphatically, “At EVG, the tools are definitely ready.”
A related question concerned the hesitancy of Cadence Design and Mentor Graphics to address the design tool issue. “It is likely they are waiting for a small start-up company to develop the tools, and then they’ll acquire them,” Vardaman said. “They have done this before.” Beyne said he is seeing a better response from the EDA vendors with regard to the EDA issues, adding, “This is a good sign that early products are coming because the EDA vendors generally don’t do anything until things are ready.”
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| 3-D interconnects represent cost sensitivity vs. performance tradeoffs. (Source: Micron Technology Inc.) |
Patti said the bigger EDA companies do not yet have a compelling reason to develop the EDA tools. “They aren’t losing business to a competitor by not having a 3-D solution,” Patti said, adding, “Designs for memory can be done with existing tools. Tezzaron doesn’t like to do it that way. It takes a lot of heavy lifting, but it can be done.” However, he said heterogeneous integration will be “impossible without better design tools.” He named R3Logic as a design house that currently has functional EDA tools for 3-D design.
The panelists were asked whether 3-D design tools should be developed under the umbrella of a consortium. There was general agreement among the panel that the design community doesn’t lend itself to a consortium format.
Finally, the panel was asked if 3-D test technology is being developed quietly, but kept under wraps because it is so important. Vardaman said that some of the probe card companies — Cascade, FormFactor and Micronics — have been working on probe card technologies. Patti said Tezzaron’s solution is built-in self-test (BIST) and self-repair. Ultimately, he said, companies will need to test the final package.
Beyne added that the various approaches to testing memory and logic are completely different, indicating that the combination of logic and memory testing would be a much more difficult task. Memory testing takes a longer time than logic testing and is performed on multiple die in parallel. For high-density TSV interconnections, inspection may be a more viable approach, Beyne said.
