Webcast: Photoresist Removal

By Semiconductor International Staff -- Semiconductor International, 5/2/2006

NOW AVAILABLE ON-DEMAND!
Originally broadcast on June 20, 2006

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Few process steps are repeated as many times in the fab as photoresist stripping, more formally known as photoresist removal. To thoroughly remove photoresist and its residues, chip companies typically use a combination of dry methods (plasma-based ashers) and wet methods (wafer cleaning tools).

Tune into this webcast to hear industry experts discuss the techniques being used to remove photoresist and its residues from front-end-of-line and back-end-of-line structures.

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Moderator

Laura Peters   Senior Editor   Semiconductor International

Panelists

   Trace Hurd, Ph.D.
   C021 Surface Prep Manager
   Texas Instruments

Trace Hurd is the Surface Preparations Manager for Texas Instruments in Dallas. He currently manages the group responsible for FEOL and BEOL surface prep development for the 65 nm node and he will be transitioning to 32 nm node development later in 2006. He has been working in wafer cleans and surface prep development at TI for the past 13 years including 3 years as a TI assignee to the Ultraclean Processing (UCP) group at IMEC. Trace received his BS degree in Chemistry from Southern Methodist University and his PhD in Chemistry from the University of North Texas.

   Richard Reidy, Ph.D.
   Associate Professor Materials Science and Engineering
   University of North Texas

Rick Reidy is an Associate Professor of Materials Science and Engineering at the University of North Texas. He received a BA from Rice University and Masters and PhD degrees from Penn State University. His research includes low-k characterization, processing, and synthesis and supercritical processing in semiconductor manufacturing. Dr. Reidy is a member and the interconnect focus team co-chair of the Surface Preparation sub technology working group of International Technology Roadmap for Semiconductors.

   Paul Mertens, Ph.D.
   Program Leader
   Ultraclean Processing Program
   IMEC

Paul Mertens is Program Manager for the Ultra-clean Processing Program at IMEC in Leuven, Belgium. This R&D program investigates cleaning technologies in collaboration with universities and leading-edge microelectronics companies including Infineon, Matsushita, Philips, Samsung, ST Microelectronics, Texas Instruments, and others. Paul joined IMEC in 1984 and has concentrated work on silicon wafer-surface quality research, including the quality of thin-gate dielectrics, defect control, effects of contamination and related metrology. Dr. Mertens is an inventor of various processes and tools related to advanced wafer cleaning, with several patents and patent-applications. He is actively involved in the organization of the biannual international Ultra-Clean Processing on Silicon Symposia (UCPSS). Dr. Mertens holds Masters and PhD degrees in Applied Sciences from the KU Lueven University.

   Mark Thirsk
   Managing Partner
   Linx Consulting

Mark Thirsk is Managing Partner of Linx Consulting, based in Mendon, Mass. He has over 20 years experience spanning many materials and processes in wafer fabrication, combined with economic and business forecasting, strategic planning, technical marketing and mergers and acquisitions. Having participated both as a user and seller of materials and equipment, as well as having intimate experience in the concerns of major materials manufacturers, Mark is well placed to bring clarity and insight into understanding markets from both a technical and commercial perspective. He has worked in the UK, Germany Belgium, and the USA, has traveled extensively in Asia, and speaks English and German. He holds an Honours B.S. in Metallurgy and Materials Science from Birmingham University and an MBA from The Open Business School.

Brian White
Member of Technical Staff
Spansion

Brian White is a member of technical staff at Spansion in Austin, Texas, focusing on contact etches. He was assigned to International SEMATECH from 2002 to 2005 working on ultra low-k etch and cleans for the 45nm and 32nm technology nodes. At SEMATECH, different types of etch, ash and clean interactions were investigated to minimize low-k damage for a dual-damascene/copper integration on 300 mm wafers. Brian has an undergraduate degree from The University of Texas at Austin and a Master’s degree from Texas State University in Physics.

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