Are Air Gaps Coming Sooner Than We Think?
Laura Peters -- Semiconductor International, 7/1/2003
What used to be considered a nuisance in previous interconnect generations may soon become an asset. Air gaps, which can form in aluminum interconnect processing due to the conformal nature of oxide CVD films, act to reduce line/line capacitance in tightly spaced wires, thereby reducing RC delay and increasing device speed. Although these gaps were usually innocuous and even helped interconnect performance, they were generally filled with a spin-on glass to prevent any reliability consequences.
Today, air cavities are being purposely designed into copper dual-damascene interconnects to effect a low dielectric constant, k. Air, more specifically vacuum, offers the greatest possible improvement in dielectric constant with a k value of 1.0. The industry is pursuing both porous low-k dielectrics, which contain air as a fundamental and uniform component of the material itself, in parallel with the perhaps more radical approach of incorporating isolated air gaps between copper lines.
One group of researchers investigating air gaps is from Philips, Motorola and STMicroelectronics. They reviewed some of the work to date on air gap approaches at last month's International Interconnect Technology Conference (IITC) in San Francisco. Laurent Gosset of Philips Semiconductors (Crolles, France) and his team from STMicroelectronics (Crolles), Motorola (Crolles and Austin, Texas), Philips Research (Leuven, Belgium) and CEA (Grenoble, France), cited advantages and drawbacks of different approaches with respect to integration, manufacturability and electrical performance. Based on recent progress, they make a case that workable air gap solutions are possible, perhaps using two different approaches to air gap formation — by removing a sacrificial material after integration or using non-conformal CVD in patterned trenches.
Interest in air gaps has grown recently as companies begin to explore the extensive integration and reliability challenges associated with porous low-k approaches. Porous low-k dielectrics include porous SiLK from Dow Chemical (Midland, Mich.), porous MSQ from JSR Micro (Sunnyvale, Calif.) or Shipley Co. (Marlborough, Mass.), or porous SiCOH CVD films from Applied Materials (Santa Clara, Calif.), Novellus Systems (San Jose) and ASM (Bilthoven, Netherlands).
Most porous material approaches are limited to a bulk k value of ~2.0, which will lead to effective k values in the stack of ~2.4. Air gaps, on the other hand, are capable of achieving lower keff (&2.0) with excellent propagation times and low cross-talk levels. The first approach, patterning trenches between metal lines and then partially filling by CVD, is perhaps the more advanced solution in terms of electrical results and integration, according to the researchers. The biggest drawback is the additional lithography and etch steps needed for trench patterning, which feature high mask cost. The aspect ratio between the width and height of the trenches must be >1, with controlled dimensions and volume to prevent breakthrough to the air gap during metal processing or because of line/via misalignment.
One such approach using silane and TEOS CVD with a SiN liner was able to achieve keff of 1.7. Air cavities have also been formed in SiOC (k=2.9) with constant aspect ratio regardless of metal space. To reduce lithography costs, a blanket dielectric etch-back process is being investigated. To protect the copper lines during dielectric etching, a self-aligned CoWP (cobalt-tungsten alloy) can be deposited on the copper, then the air gaps are formed using a non-conformal CVD process. Since the CoWP lines are wider than the copper features, the approach addresses the risk of via misalignment.
In sacrificial film approaches, the interconnect stack usually consists of a sacrificial material at the trench level and a permanent dielectric at the via level. The sacrificial material is typically removed (by reactive plasma, thermal process or wet etching) when the interconnect stack is complete. One sacrificial air gap approach removes a carbon-based layer after an oxygen gas has diffused through a SiO2 bridge layer and reacted with carbon under the bridge to form the gaps. Some USG can be left below the metal lines, but there are issues associated with a 450°C anneal in O2 on the metals.
Polymer sacrificial materials can be removed at each metal level using 400-425°C anneal in N2. However, this approach can exacerbate via misalignment issues. Alternatively, a single thermal treatment can be performed on the whole stack, which also improves the mechanical stability of the structure. The industry may pursue newer sacrificial materials with higher decomposition temperatures to reduce thermal budget constraints.
The Crolles2 Alliance is pursuing an approach that successively deposits SiLK as the permanent dielectric and USG as the sacrificial layer. Because these materials and processes are known, less process development work is necessary. After the final interconnect module is completed, the USG is attacked and decomposed by dilute HF that diffuses through the SiLK. The approach features a less stringent lithography mask. As with most sacrificial approaches, integration of a self-aligned diffusion barrier on copper is needed. The group says this is the only technique that simplifies the diffusion from the annealing ambient or liquid phase of the etchant while facilitating the out-diffusion of the reaction product.
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