High-k/Metal Gates Solution to EOT/CET Challenge
Peter Singer, Editor-in-Chief -- Semiconductor International, 5/1/2004
The International Technology Roadmap for Semiconductors (ITRS) identifies two key metrics related to the gate dielectric of a transistor: equivalent oxide thickness (EOT) and capacitive effective thickness (CET). The definitions for these metrics are somewhat abstract, but the ability to keep up with these metrics as devices are scaled down will require a major change in materials used for the gate dielectric and gate electrode.
EOT is defined as the thickness of SiO2 that would produce the same capacitance-voltage curve as that obtained from an alternate dielectric system. Because the dielectric constant of the material is seldom known with any certainty, the EOT must be determined from an electrical capacitance measurement. The intent is to provide a metric that does not depend on other quantities (e.g., type of electrode, electrode work function, or substrate doping). CET is an effective thickness that depends on other quantities such as type of electrode, electrode work function, substrate doping, and gate voltage of measurement.
The solution to lowering EOT and CET lies in high-k gate dielectrics and metal gate electrodes. The industry has zeroed in on hafnium-based materials as the most suitable high-k gate dielectric; the type of metal used for the gate electrode depends on whether the device is built on a bulk substrate (where n- and p-type metals are required) or a more confined-silicon approach, such as fully depleted SOI or 3-D designs such as the finFET.
Recently, researchers at IMEC (Leuven, Belgium) reported that they successfully demonstrated the use of high-k dielectrics and metal gates to achieve EOT &1 nm. Using TiN or TaN gates and HfO2 as the dielectric, they fabricated devices with 0.8 nm EOT, for nMOS (8.2 Å EOT) and pMOS (7.5 Å EOT) transistors (Figure ). The metal-gated devices outperformed their polysilicon-based counterparts in terms of electrical performance parameters, including high conductance, low leakage and reduced threshold-voltage instabilities. Besides the elimination of gate depletion, the metal gates enhanced high-k scalability and significantly reduced gate leakage by up to three orders of magnitude. Transistor drive current also improved significantly.
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Figure-of-merit for both nFET (left) and pFET (right) performance, representing gate leakage as a function of performance. The symbols represent performance trend lines for poly/SiO2, poly/high-k and metal/high-k gate stacks. (Source: IMEC)
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To realize sub-1 nm EOT scaling, appropriate interfacial oxide control, both prior to and during high-k deposition, was applied. The lowest EOT values were typically obtained using a "minimal interface approach" (i.e., minimal EOT contribution). To achieve this, scaled chemical oxide interfaces with controlled thickness and precisely controlled deposition and annealing conditions were used. HfO2 was deposited by atomic layer chemical vapor deposition (ALCVD, or ALD).
If that sounds like it might be difficult to reproduce in a manufacturing environment, you're right. Some companies will make a trade-off and go with materials that result in lower overall k values, according to Stefan DeGend of IMEC. "Companies that are interested in more standby power applications, have less aggressive EOT scaling requirements, and they can definitely get away with nitrided hafnium silicates with a k value of 10," he said. "Companies that are interested in high-performance applications, in order to achieve sub-1 nm EOT, need higher k values and therefore are focusing more on hafnium oxide." Hafnium oxide is more difficult to work with because it can crystallize with the temperatures typically found in IC processing, which results in higher leakage current along grain boundaries. Silicates are more amorphous, and nitrogen is used to stuff grain boundaries.
Problems with threshold voltage (Vt) degradation have also been seen with high-k. The Vt shift problem is more severe with hafnium oxide than with hafnium silicon oxynitrides or hafnium silicate dielectrics, said Thomas Schram of IMEC. "The problem of the Vt control in our view is related to materials interaction and related to the interaction between hafnium and polysilicon, giving what you might call a defective change in the work function of your gate stack. It turns out that the metal gate is probably going to come in with high-k at the same time for the high-performance (devices), and for the low standby power probably in later generations."
For additional information on wafer processing, go to www.semiconductor.net/wafer
Notable Changes to the 2006 ITRS
01/31/2007New Approaches to Fabricating Metal Gates
02/09/2010High-k, Metal Gates a 'Go' for 45 nm
02/28/2007
