IEDM Panel: Processing Costs Headed Up
With more expensive tools and new process modules coming, IC manufacturers will struggle to maintain the cost-per-function reductions that have broadened the market for semiconductors. The likely introduction of 3-D interconnects, vertical transistors and EUV lithography all will add pressure on wafer processing costs, experts said at an evening panel discussion at the International Electron Devices Meeting going on in San Francisco this week.
David Lammers, News Editor -- Semiconductor International, 12/17/2008
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Worried about rising costs, manufacturing managers laid out their visions of how IC manufacturing will progress over the next decade at an panel discussion Tuesday evening at the International Electron Devices Meeting (IEDM) in San Francisco. The next decade will see ~$10B fabs using extreme ultraviolet (EUV) and maskless electron-beam lithography, cranking out microprocessors with 12 billion transistors on each die, one panelist predicted.
Moderated by Hans Stork, CTO at Applied Materials Inc. (Santa Clara, Calif.), the discussion was influenced by a stronger-than-normal downturn that prompted Takashi Yoda, a manufacturing manager at Toshiba Corp. (Tokyo), to express hope that “we do not have an excessive shakeout of our suppliers. We need to have a strong and balanced industry.”
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| Craig Sander, AMD |
Craig Sander, in charge of process R&D at Advanced Micro Devices Inc. (AMD, Sunnyvale, Calif.), said the question on many people’s minds is whether the semiconductor technology is slowing down. “The answer is: Not yet, but it soon will be,” he said.
The industry will stay on its two-year cadence through the 22 nm generation, and then see a slowdown after that, Sander told several hundred IEDM attendees. “Costs are getting higher each generation. The cost of developing a process goes up by 40% for each generation, which means it is effectively doubling every other node. And the rising cost of processing the wafers won’t be offset by the density increases” gained from moving to the next node.
Faced with a likelihood that expensive cost adders such as through-silicon vias (TSVs) and vertical transistors will be needed to keep technology on track, the industry must work harder to reduce costs in other areas. Sander said test costs are high, arguing, “There is a lot more for the industry to do in advanced testing. In the factory, we can gain many advantages by reducing the cycle times.”
Fabs are getting bigger, in part to reduce construction costs. Micron Technology Inc. (Boise, Idaho) estimates that today’s fabs need to process >120,000 wpm to be efficient. A single fab running 180,000 wpm saves a significant amount in construction costs compared with building three 60,000 wpm fabs, said Ceredic Roberts, a Micron manufacturing executive on the panel. To absorb capacity for memories, Roberts said, “we need a demand surge. Oversupply must be corrected.” He noted that solid-state disk drives are gaining traction, and more silicon will be required in electric cars, green energy production, and other emerging areas.
Bill Arnold, chief scientist for lithography tool vendor ASML (Veldhoven, Netherlands), said ASML will do its part to improve fab productivity by incorporating a maglev-enhanced stage in its next-generation 193 nm immersion scanners that will boost wafer throughput to ~200 wph. However, when EUV lithography is introduced starting in 2011, throughput for those scanners will drop to 60 wph. The next generation of EUV scanners will improve throughput to 100 wph, and the numerical aperture (NA) will increase to 0.32, up from the 0.25 NA of the original EUV scanners. One participant at the session estimated that fabs will need four EUV scanners for critical-layer lithography, at ~$70M each.
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| TSMC sees fabs costs going to $10B by 2015. |
John Lin, director of the manufacturing technology center at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan), predicted that leading-edge fabs will cost ~$10B in 2015, up from ~$4B now. The number of transistors for a microprocessor will increase from ~1.4 billion now to ~12 billion by 2015, and critical dimension (CD) control will tighten from 1.5 nm to 0.7 nm over the next seven years.
Both EUV and maskless lithography will be introduced to TSMC’s fabs, and manufacturing software will be called upon to provide “flexible capacity,” he said. Now, a fab can process 1000 wafers per month with six operators on the payroll, but the ratio will shift to one operator per 1000 processed wafers, he said.
“Double patterning, 3-D interconnects, finFETs — all of these will increase costs significantly,” Lin said. “Introducing 450 mm wafers will reduce costs somewhat, but not enough.”
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I doubt EUV or maskless will be ready since there are still too many unsatisfied requirements like throughput and defects. Plus there is no real resolution advantage at 22 nm and below, when you figure in the ubiquitous secondary electrons.
looking at big picture - 12/18/2008 3:12:00 AM CST -
This year's IEDM looks pretty lame. Glad not to have gone.
lol - 12/18/2008 3:00:00 AM CST
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