Source-Mask Optimization Continues on Track
IBM and Mentor Graphics provided an update on their effort to develop source-mask optimization (SMO) during the SPIE Advanced Lithography conference. SMO is targeted at the development of a number of computational scaling technologies that would enable pixel-level programming of illumination sources, extending 193 nm immersion lithography to 22 nm.
Alexander E. Braun, Senior Editor -- Semiconductor International, 2/27/2009
Last September, IBM (Hopewell Junction, N.Y.) and Mentor Graphics (Wilsonville, Ore.) announced an initiative to develop source-mask optimization (SMO) in time for the 22 nm node, a move in part prompted by the slow development of alternative methods such as extreme ultraviolet (EUV) lithography.
The SMO effort is targeted at the development of a number of computational scaling technologies that would, among other capabilities, enable the pixel-level programming of illumination sources. SMO is expected to enable the extension of 193 nm immersion lithography, to deliver density scaling for 22 nm.
Compared with the alternatives, the technology is expected to reduce manufacturing costs while improving turnaround by improving process windows (dose, focus, mask error). SMO is being developed like no another optical proximity correction (OPC) product ever was, by a globally integrated team. Software development and silicon validation are taking place simultaneously, and the resulting solutions will be made available through IBM and Mentor.
At the SPIE Advanced Lithography conference in San Jose this week, representatives from IBM and Mentor Graphics said they are currently transitioning code from the research prototype into Mentor’s Calibre design-to-silicon commercial product. It appears everything is on track to meet 22 nm development schedules for IBM and its technology partners.
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| Charles Albertalli, Mentor Graphics |
“Every two nodes, we end up trying to find a new way in which to use our software and RET [resolution enhancment technique] capabilities to overcome the gap in the k1 parameter that the hardware companies cannot provide,” said Charles Albertalli, marketing director for Calibre RET and MDP, Design to Silicon Division, at Mentor. “So, until we get to EUV, 193 is it for optical lithography. The NA is at 1.35, and that doesn’t seem as if it’s going to change.”
Albertalli added that at the current state of the technology, insofar as process nodes and the capability that the hardware can provide are concerned, there is a significant gap. “It seems as if every two years we have to come up with something new to address that gap. At 65, 45 nm, we went from sparse to dense OPC. We solved the advent of hardware acceleration to be able to manage the turnaround time. Now, at 22 nm, even dense OPC isn’t enough; we need to take advantage of every degree of freedom in the optical system and in the capabilities that we have in software development to try to minimize the application of double patterning, which obviously has significant cost implications for design and for the industry.”
At this point, it would seem that SMO is the way to go, although it is no simple undertaking. One reason is that it is computationally intensive even by today’s standards. But as Albertalli put it, “Fortunately, with IBM, we have a resource that gives us the opportunity to develop onto the most advanced hardware platforms available, and there are some great advances in that domain that make this possible. It would not have been possible five years ago.” He recalled how the company took advantage of the Cell platform two years ago with 45 and 32 nm, bringing turnaround time down by a factor of 8. “We will have similar capabilities available to us at 22 nm that will help to manage the turnaround time and computational complexity of the solution,” he said. “We’re taking RET to the next level by looking at the source, new degrees of freedom on the mask, and taking advantage of new computational capabilities to put together a complete solution.”
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| Timothey Farrell, IBM |
Timothy Farrell, manager of IBM’s Computational Lithography Project Technology Group, emphasized the fact that EUV lithography will not be available in time for the 22 nm node, pointing out that the additional benefits that were derived from 193 nm immersion lithography have flattened at the 32 nm node. “There’s no new inherent resolution capability,” he said. “The double exposure techniques that we are being promised would be too expensive — both from a manufacturing and design aspect. We need an alternative, and SMO is it.”
Farrell said current data indicates that it is going to be possible to cut the amount of double exposure levels, with a possible 20-35% reduction in the number of critical exposure masks. “It also looks like we will be able to reduce the number of design constraints in moving to 22 nm and working in such a low k1 environment. At the same time, it enables the setting up of a platform that will also be extendable as we push to 16 nm, which will have to do double exposure.” He added that SMO should facilitate it, optimizing each of the masks against what is, essentially, a &0.25 k1 that must be enabled by pitch splitting. By that time, this will be a mature technology. And by then — perhaps — the industry will not still be waiting for EUV.
Listen to a podcast interview with Farrell and Albertalli (Runtime: 10:41)
