TI Pushes Junctions in 45 nm Transistors
David Lammers, News Editor -- Semiconductor International, 2/7/2008
Texas Instruments Inc. (TI, Dallas) technology managers said improvements to junction engineering, supported by millisecond annealing techniques, play a key role in TI’s 45 nm transistor technology, now winding its way toward mass production in the second half of this year.
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| Ben McKee, VP of CMOS development, TI |
Ben McKee, vice president of advanced CMOS development, said the biggest challenge at the 45 nm node was to control leakage while scaling the silicon oxynitride (SiON) gate dielectric by several angstroms and shortening the gate length.
McKee said TI engineers created “significantly more abrupt junctions, without increasing leakage. There are continual improvements to the implant tools which allow that, but the bigger area of change is how we do the activation and diffusion of the implants. We went to millisecond anneals pretty extensively.”
He declined to discuss how flash and/or laser annealing techniques were implemented, saying that is part of the proprietary knowledge of TI’s main foundry partners that have made the sample 45 nm parts. Although TI used immersion lithography for selected critical layers, it avoided costly embedded silicon germanium (eSiGe) stressors or high-k gate dielectrics; those technologies will be introduced at the next node for wireless ICs, he said.
| TI's 45 nm NMOS (left) and PMOS transistors use abrupt junctions and 38 nm gate lengths, while keeping leakage at a minimum. |
TI presented its 45 nm progress at this week’s International Solid State Circuits Conference (ISSCC) in San Francisco, including a discussion of a wireless baseband and applications processor that moves into volume production in the second half of this year. That 45 nm custom chip includes an ARM11 processor running at ~840 MHz. The 45 nm transistors support a 55% performance increase, along with a 63% reduction in power consumption, he said.
McKee said TI used body-biasing techniques to dynamically reduce leakage or boost performance, rather than creating transistors with different fixed threshold voltages (Vt). By controlling the voltage applied to the bottom gate, a reverse body bias raises the Vt to reduce leakage, while in other areas a forward body bias can be applied to lower the Vt and speed the transistor up.
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| Brian Carlson, strategic marketing manager, TI |
Brian Carlson, strategic marketing manager for TI's wireless business, said, “Other companies may use different transistors with a higher threshold voltage, but that requires additional process steps. This is a cost-effective way to achieve lower leakages instead of using standard off-the-shelf transistors, where people have a low threshold voltage or a high threshold voltage transistor. We don’t need extra threshold voltage to accomplish this, and we don’t have to add a bunch of levels or extra masks.”
McKee said the use of body biasing and a memory technology called Retention ‘Til Access (RTA), which retains a bit’s state at low voltages, required close cooperation between TI’s design and technology development teams.
“This is a very cohesive tuning of the power reduction techniques. We target the performance and leakage characteristics of the transistor to make sure the power management techniques and the silicon work together,” McKee said.
Foundry collaboration at 32 nm
TI internally developed its 45 nm technology. At the 32 nm node, TI’s foundry partners will lead technology development, working in cooperation with the company's technology development team. Last year, TI laid off ~500 technologists and technicians as part of the shift in strategy toward foundry technology development.
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| Tom Thorpe, VP of external development and manufacturing, TI |
Asked if TI will be able to so closely tune its designs to the 32 nm silicon being developed in Taiwan, Tom Thorpe, vice president of external development and manufacturing, said, “That absolutely will not change. It can’t change very much if we are going to keep on our schedule.”
He said that TI’s competitors “already have demonstrated collaboration with their foundry partners, creating fairly aggressive products on a competitive time scale. Working with foundries over the years, we have developed a strong base of how to operate on the leading edge. And we have kept a lot of those TI people, even though we have restructured the model. The proof of that is that we will be releasing 32 nm test chips into those foundries fairly shortly on the same schedule as if we were developing internally.”
McKee said keeping power consumption under control requires a highly interactive process, developing design techniques and transistors that meet the leakage and speed characteristics. “We specify all the transistors [in the memory bits] so they respond with the desired leakage characteristics, as well as speed, when they are turned on. This involves a lot of choices, including which aspects of leakage are critical in which state. How we tune the choices, the threshold voltage, the junction technology, the gate dielectric — all are chosen very carefully to play together. And the techniques play a little differently, depending where the leakage is going to or coming from.”
Carlson said, “This is how we keep our competitive edge, though who we work with closely is changing, so we can focus on design and other areas where we can add value.”
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