Moore’s Law — A Holistic and Economic Approach
Like a prophet descending from a holy mountain, Bernard Meyerson presented a new gospel of Moore’s Law in his keynote address, “Semiconductor Technology: A Convergence of Technology and Business Models,” given yesterday on the keynote stage in the West Hall.
Alexander Braun, Senior Editor -- Semiconductor International, 7/16/2008
Like a prophet descending from a holy mountain, Bernard Meyerson presented a new gospel of Moore’s Law in his keynote address, “Semiconductor Technology: A Convergence of Technology and Business Models,” given yesterday on the keynote stage in the West Hall.
| Bernard Meyerson, Fellow and CTO, IBM Systems and Technology Group |
The IBM Fellow and CTO for IBM Systems and Technology Group (Armonk, N.Y.) dissected Moore’s Law, pointing out that it has always referred to economy, not technology. “People see it dealing with performance and power — nonsense. Moore’s paper dealt with industry economics, not technology. He said, ‘Look, you got to double what you put on a chip roughly every 12 to 18 months or we don’t survive.’ This is an economic, not technological, imperative.” More than once during his presentation, Meyerson emphasized that the enabler of the industry’s success has been classical scaling, which describes how to make the technology smaller. It is not just a matter of shrinking a transistor. There is a recipe for it, which, if followed, keeps the chip’s power density constant, regardless of what is added.
The recipe is approaching an atomic barrier where critical layers, such as the gate dielectric, are only 10 Å thick, about five atoms. “Atoms don’t scale,” Meyerson said. “Gate oxide cannot be made thinner, so people left it constant for several generations. However, if you had a 1 cm2 10 W chip in 1960 and its density increased by a million, it is now a 10,000,000 W chip.”
| This light-emitting single carbon nanotube transistor is a candidate for a ‘next-generation’ switch. (Source: IBM) |
Power in general, not just for chips, is a crisis. In the IT world, a study determined that there has been a slow single-digit growth rate in servers over the last eight years — ~5% a year, about $50B spent yearly worldwide on new servers. However, the electric bill to cool and power them has grown at 800%. Extrapolating from this, by 2012, people will spend as much for electricity as in buying servers.
Meyerson argued that scaling will not work for the future. “You’ll get something that burns more power, costs more, and is slower. Here’s where you use things like SOI and strained silicon, dual-core technology, immersion lithography, SiGe chips, high-k, 3-D chip stack, and air gap.” All of these innovations are traceable to fundamental science R&D. Air-gap dielectrics are done using lab-developed self-assembly of chemical materials. “We use nanotechnology to build what is standard technology years later,” Meyerson said. “This is why many are getting out; few are willing, or can, make the R&D investment.”
Meyerson addressed density from lithography’s perspective. Unsurprisingly, he stated that extreme ultraviolet (EUV) will not be ready for the 22 nm logic node, outlining other possibilities. “We’ve gone from 436 to 193 immersion,” he said. “If we’re stuck there, we’ll have to find another way.” Another way is what IBM calls computational lithography. “You digitally compute the light paths, impacts and interferometric effects from the source to the wafer surface and into the actual resist and do a rigorous model. You segment the source into thousands of almost pixels and individually light them according to an optimization routine, so features can be dramatically cleaned up, even at 22 nm.”
The problem with this integrated optimization is that the predictive model is indescribably difficult computationally, requiring modeling from first principles. “We run a model through our supercomputers to look at the light just under the mask, the light just over the photoresist, and the development reactions within the photoresist to get from the design to the actual prediction to actual wafer results which, at 22 nm, are gorgeous,” he said. Although difficult, this shows a path to 22 nm — combining “conventional” lithography with supercomputing.
Meyerson sees shrinks ending within a decade. “Density will improve through 3-D stacking and the application of optical technology,” he said. “Some version of Moore’s Law will be followed. We didn’t foresee it would require a vertical perspective. There will be a tremendous focus on 3-D system architecture — logic, cache, memory, I/O subsystem — all optimized and integrated in a single stack.”
Key to Meyerson’s presentation was the fact that the industry can no longer tackle just one element — high-k dielectric, for example — to continue on its path to more complex devices; it must think holistically about all problems and increase pre-competitive R&D cooperation.
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