Reducing Test Costs, Throughputs
At yesterday’s Test, Assembly & Packaging TechXPOT’s “Yield Management” session, various presenters demonstrated the necessity of reducing rocketing test costs. Overall, the presenters concentrated on the fact that testing becomes more difficult and costly as chip complexity continues to grow and device average selling prices (ASPs) shrink.
Alexander Braun, Senior Editor -- Semiconductor International, 7/16/2008
At yesterday’s Test, Assembly & Packaging TechXPOT’s “Yield Management” session, various presenters demonstrated the necessity of reducing rocketing test costs. Overall, the presenters concentrated on the fact that testing becomes more difficult and costly as chip complexity continues to grow and device average selling prices (ASPs) shrink. There was a consensus that the only way yield and productivity could be improved, and time to market met, is through the best and most efficient use of test equipment. It was also shown that a crucial part of this is how the data produced by test equipment is handled and processed. Several strategies were put forward on how these concerns could be addressed. As stated during one of the presentations, “In the past, test was a BEOL operation, a disconnected activity, sometimes viewed as having little value added. Today, and in the future, test will be the central hub for product optimization.”
| Debbora Ahlgren, Vice President and Chief Marketing Officer, Verigy |
In her presentation, “Improving Time to Yield,” Debbora Ahlgren, vice president and chief marketing officer for Verigy (Cupertino, Calif.), touched on the fast rate of innovation. “When we crossed the 100 nm threshold, we found out that design now affects yield,” she said.
Ahlgren pointed out that profits are being driven by the consumer market, and are increasingly dependent on time to market. “On top of all this,” she said, “the new processes being introduced are highly sensitive to equipment variation, and we find that more failures are caused by design/process interactions.”
All of these factors require more aggressive design for test (DFT) techniques, because this can reduce the complexity of test requirements and provide for higher fault coverage. “Structural test is required to ‘probe’ inside the die,” she added.
“A Five-Minute Approach for Probe Yield Improvement,” presented by Terence Collier, president of CV Inc. (Plano, Texas), pointed to the considerable costs of poor probing. According to him, two significant items can impact post fab yield: test hardware and bond pad conditions. “Removing the highly resistive oxide layers that can form on surfaces improves yield, extends probe card life, minimizes reliability issues, and eliminates process control concerns,” he said.
Collier gave several good reasons for carefully cleaning the wafer, stating that problems in test often arise not from the probe card itself, but from dirty bond pads. “Five minutes of cleaning is well-worth it if it saves hours or extra probing to recover die,” he said. He added that this brought with it the added advantage of a reduced reliability risk and better process control because damaged pads can lead to customer returns. Collier described a cost-effective solution that removes these oxides without affecting the base metals, mentioning that an oxide-free surface probes better and improves assembly yield.
Stephen Pateras, senior director, Strategic Technology, LogicVision Inc. (San Jose), reviewed the subject of “Optimizing Test Equipment Through BIST,” during which he emphasized how built-in self test (BIST) can optimize test resources. “There is a need for test time reduction,” he said, “which requires higher throughput and higher parallelism.” Pateras showed how BIST leads to a reduction in automatic test equipment (ATE) costs by cutting down on performance requirements, providing greater multi-site capability, as well as high test portability, which allows tester remix, freeing the testing procedure from specific platforms. “One of the results is test time reduction, which leads to higher throughput and parallelism. Another benefit is reduced fixturing costs due to the need to contact fewer pins.”
For all of this, a more comprehensive BIST infrastructure is required for memory to provide at-speed test, diagnosis and repair of embedded memories; for logic, again for at-speed test and the diagnosis of random logic; and lastly, for the accurate test an characterization of high-speed I/O. Pateras’ focus and message were that test costs continue to grow and BIST provides a road to lowering costs, test times and capex expense.
Other presentations in the session were “Ensuring Known-Good Advanced Package — The Role of Automated Wafer Inspection,” by Udi Efrat, Camtek (Migdal-Haemek, Israel); “Adaptive Test — All Aboard,” by Keith Arnold, CTO and vice president, Worldwide Applications Engineering at Pintail Technologies (Plano, Texas); and “Semiconductor Test — From Back-End to Center Stage,” by John Bearden, who is in charge of U.S. Business Development for Optimal Test (Nes-Ziona, Israel).
Standards for Test
12/01/2007Reduced CapEx for Test
07/11/2008Lithography, Test Among Cost Challenges
11/08/2007
