Demand Spikes for Multi-Site Testing
Multi-site testing of SoC devices is now emerging as a major trend to drive down the cost of test. Test vendors also are developing adaptive testing: leveraging the previous test results from a device as it goes through various test steps.
Sally Cole Johnson, Contributing Editor -- Semiconductor International, 1/22/2009
Amid the current worldwide economic instability, with semiconductor manufacturers reluctant to invest in capital equipment, automatic test equipment (ATE) vendors are being tested to their core. Their customers are demanding cost minimization solutions for system-on-chip (SoC) devices — focusing on multi-site testing.
Multi-site testing involves a single tester touching down on multiple devices at the same time as the handler sequences multiple devices through a tester. Rather than testing the devices one after another, multi-site testing is like a freeway with multiple lanes where different tests are running in parallel to increase throughput, said Dave Armstrong, SoC director of marketing at Advantest America (Santa Clara, Calif.).
It’s not a new trend in the industry, but demand for multi-site testing has increased over the years. Now that cost minimization is key, adding another eight lanes of testing to a tester’s capabilities reduces the fundamental baseline costs for test. “Multi-site efficiency is going to be really critical in 2009,” Armstrong said. “Customers want to make sure that all the lanes in their ‘multi-lane highway’ are active all the time. Multi-site efficiency, test times and the number or test sites are all parameters that will impact the semiconductor industry strongly in 2009.” Every second on the tester counts, and every tester pin must be used.
Higher multi-site count challenges
|
| Special techniques greatly minimize the noise in multi-site RF device under test (DUT) boards. (Source: Advantest) |
There are at least four major hurdles involved in shifting to higher multi-site counts, according to Armstrong. The first challenge is high-density pin resources. SoC devices have 600-800 pins, or more, today. If you want to do a four-site test, you’ll need up to 4000 pins on the tester. “If you look at the trends, the pins/device under test (DUT) aren’t growing much,” Armstrong noted. “Some people are still doing 16-pin devices, and obviously they want to do 256 sites, which doesn’t work out to be that many pins — 4000. The bottom line is that a large number of pins is a requirement.” With analog and RF testing, higher pin densities are also required for multi-site testing.
The second challenge is a test system that can effectively use all these resources without a loss of multi-site efficiency. “For multi-site efficiency, you need to keep all those 2000-4000 pins active, busy testing parts. In a multi-lane highway, you can improve the transport efficiency by reducing the distance between the cars. Similarly, in ATE we need to keep each socket active all the time. A multi-site efficiency of below 90% is not very good these days. In fact, if your multi-site efficiency is 50%, you could just as easily buy a new tester. In the high 90% range is where everyone wants to be — if not at 100%, which is a panacea I don’t think anyone has achieved yet.”
The third challenge is finding a way to interconnect the many resources to the various devices without sacrificing performance, Armstrong said. “This is very important in the RF and analog world, and it’s greatly complicated by a bunch of digital pins,” he added. “If you try to route all of your digitizers and AWGs from a single location on the DUT board, not only will you end up with very different signal routing per DUT, but you’ll also end up with different noise floors on the different signals. The problem only gets worse with RF interconnects. In addition to the signal routing problem, it’s necessary to achieve high isolation between the various test sites.”
Handler X and Y pitches also need to scale with higher multi-site counts. Wide pitches and large DUT board areas are needed, according to Armstrong. “The natural result is that multi-DUT solutions are becoming more test-cell-centric,” he said.
The fourth challenge is that higher multi-site counts require a large testhead that can accommodate more modules to scale with future higher-multi-DUT solutions. “One of the key things to worry about here is liquid cooling,” Armstrong said. “A lot of circuitry goes into the system to get high-density pin resources. The industry needs to do this without making the testhead so big that it’s hard to maneuver.” A high level of integration is necessary, because the best way to cool the high-density ATE pin electronics is through immersion-based cooling.
Adaptive testing
Perhaps an even bigger challenge is how the ATE handles different test flows per DUT. Adaptive testing is leveraging the previous test results from a device as it goes through various test steps at a semiconductor fab, in order to focus the testing on likely problem areas.
“If you can leverage the knowledge from the second and third test steps for the fourth step, it can improve the overall quality of the test and it can also streamline the testing in the fourth step,” Armstrong said. “You might even be able to reorder the tests based on the knowledge gained from the previous steps. For instance, you may discover that the threshold voltages are high. If you know this, when you get to wafer probe, you might prioritize test 23, which is a test that would be impacted by that problem to execute earlier in the flow. This allows you to shorten the test time because you can more quickly disposition the parts.”
Armstrong believes adaptive testing can revolutionize the industry. “Three years ago, people were trying adaptive testing — without much success. Right now, people are doing it and seeing significantly faster test times, and they’re finally able to focus the test on the device in the socket. Many tests can be eliminated. It’s very challenging for ATE vendors to keep generating different test sequences in adjacent test sockets without sacrificing multi-site efficiency.”
Short-term outlook
Right now, Advantest is seeing opportunities with two SoC customer types. There are customers with RF and power management IC (PMIC) needs who are looking for higher site counts and multi-site efficiencies. In addition, there are customers with already-installed SoC test systems now looking to add more parallel test sites to lower their cost of test and improve efficiency.
Multi-Package BGA
02/09/2010Wire-Loop Shaping in Multi-Tier Packages
02/09/2010test
05/18/2006Wafer Provides Standard for Dielectric Test
07/31/2004Mixed-Signal Tester
06/15/2001
