3-D ICs Enter Commercialization

Among many manufacturers -- Micron, Toshiba, STMicroelectronics, Intel, Chartered Semiconductor and TSMC -- 3-D integration using through-silicon vias is imminent.

Philip Garrou, Microelectronic Consultants of North Carolina, Research Triangle Park, N.C. -- Semiconductor International, 11/1/2008

Part 1 of this article, "How Might 3-D ICs Come Together?", reviewed the various processing options for fabricating 3-D stacked devices. Part 2 examines the activities of companies commercializing 3-D through-silicon via (TSV) technology.

First applications

Traditional device scaling will reach its physical limit within the next 10–15 years, leaving little time for the development of new device structures such as carbon nanotubes (CNTs), spintronics and molecular switches. Therefore, while the integration of copper and low-k dielectrics continues, mounting concerns on device and system levels have industry leaders looking for new assembly methods to fill a short-term need. At the forefront are 3-D ICs, which can shorten interconnect lengths and lead to improvements in latency, power consumption and memory bandwidth.

Current 3-D IC integration is characterized as a system-level architecture in which multiple layers of planar devices are stacked and interconnected using TSVs in the Z direction. Initial 3-D applications will likely begin with CMOS image sensors (CIS), then DRAM, memory on logic and, by 2014, heterogeneous integration (Fig. 1). This follows a pattern of ever-smaller TSVs and perhaps ever-thinner silicon layers.

1. The first 3-D application will be CIS devices. Over time, applications will require TSVs to be thinner. (Adapted from Leti)

The use of the sensor devices has skyrocketed in recent years, fueled by the growth of cameras in cell phones. To eliminate traditional bump-based interconnect solutions, CIS must be mounted face up, making TSV, which permits this orientation, the smallest and most cost-effective packaging solution available today. The success of CIS has had the effect of generating significant commercialization interests for the TSV technology. Similarly, the viability of 3-D bonding technology was spotlighted when DRAM-to-logic (face-to-face chip) bonding was first demonstrated and the chips subsequently commercialized and used in the 2005 Sony PlayStation¹ and numerous MEMS applications.

The first-generation CIS products are devices based on wafer-level packaging (WLP) with TSVs etched from the back of the chip to the I/O pads, with subsequent backside redistribution. All roadmaps are indicating that next-generation products will be bonded to DSPs, thus forming true stacked 3-D structures, as exemplified by the Oki/Zycube roadmap (Fig. 2).²

2. The Zycube/Oki CIS packaging roadmap indicates that a majority of server DRAMs will require TSV packaging solutions. (Source: Zycube)

Over the past year, the amount of interest in CIS TSV technology has clearly been on the rise: Toshiba announced CIS TSV manufacturing capacity,³ an agreement between Oki and startup Zycube established a plan for 10,000 wpm capacity on an existing Oki line by March 2009, STMicroelectronics announced volume production "...by the end of June 2008,"⁴ and Micron spin-off Aptina claimed that its latest CIS will use TSV technology.²

Future demands

Clearly, the need for speed will dictate the technology used in fabricating next-generation stacked memory devices. By 2009, DDR3 will require speeds exceeding 1333 Mbps DIMM, and it is expected that only TSV technology will be able to meet that requirement (Fig. 3). Micron's Kyle Kirby concurs, saying, "The industry as a whole and Micron specifically will be forced to move to 3-D TSV stacking technology in order to meet DDR3 and DDR4 required device performance in the future."⁵ Biao Cai of IBM's server division agrees.⁶ And by 2013, it is expected that a majority of server DRAMs will also require a TSV packaging solution (Fig. 4).

3. To meet DIMM speed requirements, TSV technology currently presents an edge over other technology options. (Source: Micron)

4. The trend to high speeds in server DRAMs will likely require TSV packaging solutions for a majority of DRAMs by 2013. (Source: Micron)

Memory on logic

Conventional 2-D architectures for processors have L0 and L1 caches on the same die as the processor, with the L2 cache on a separate die. Processor-to-cache interconnections thus consist of long lines — in some cases causing multiple clock cycles to pass before data moves from one end to another.

The tremendous bandwidth needed to avoid such latency issues in the multicore processor systems of the future can likely only be addressed by TSV, where interconnect length can be reduced. This is why die-to-wafer stacking is probably the best choice for logic+memory applications. Different sized die can be stacked together, and pre-testing both microprocessor and memory is relatively straightforward, allowing the use of known good die (KGD).

The advantages have led chipmakers like Intel to look at both logic+memory stacking, which includes stacking cache or main memory onto a high-performance logic device; and logic+logic stacking, which involves splitting a logic area between two or more layers and requires much tighter pitches than logic+memory stacking.

5. This cross-section shows an Intel SRAM chip Cu-Cu bonded to a processor and connected by a 5 µm TSV. (Source: Intel)

In 2006, for example, Intel displayed a 300 mm wafer of 80-core microprocessors using TSV to mate processor cores directly to SRAM,⁷ noting that it was TSV technology that allowed them to overcome latency issues and achieve required information transfer rates between the processor and memory. Such chips would be in production within five years, said CEO Paul Otellini, adding, "TSV will make for an enormous increase in overall system performance, likely even greater than the inclusion of 80 cores on a single die." It is possible that TSV could be used in a variety of Intel chips — not just the "terascale" chip.

In published work, Intel has shown copper-copper bonding for mechanical and electrical interconnection. Figure 5 shows a cross-section of an SRAM chip Cu-Cu bonded to a processor and connected by a 5 μm TSV through a 10 μm memory chip. Through such memory-on-logic bonding, Intel has realized a 66% power reduction in average bus power (due to reduced bus activity), and demonstrated peak temperature increases of ~2°C when stacking DRAM on a 92 W microprocessor. This is because DRAMs consume very little power and the hotter processor remains next to the heat sink (Fig. 6).⁸

6. This illustration depicts a packaging configuration using TSVs wherein a CPU is stacked on a DRAM/SRAM chip. (Source: Intel)

Heterogeneous integration

7. A 3-D stacking scheme for heterogeneous integration illustrates the integration of incompatible technologies. (Source: Zycube)

3-D architecture begins with the production of full wafers of a specific function, such as DSPs, SRAM, DRAM, etc. These are then thinned, aligned and vertically interconnected (chip-to-wafer or wafer-to-wafer) to create a functional device. By allowing the integration of otherwise incompatible technologies, the 3-D concept offers significant advantages in performance, functionality and form factor. In some sectors, this has become known as "heterogeneous integration," shown pictorially in Figure 7. Other technologies that could be conceivably included in the stack are antennae, sensors, power management and power storage devices.

For example, it is well known that the power amplifiers used in all cell phones are built out of GaAs. In reality, only certain circuits need to be fabricated in GaAs. 3-D integration would allow bonding of small patches of GaAs to silicon CMOS circuitry that, when bonded, comprise a completed circuit. This would result in substantial cost reductions. Such technology has obvious defense applications, and indeed is known as COSMOS (compound semiconductor on silicon) in the military sector.⁹

The evolving infrastructure

Several different paths can be taken to implement 3-D IC integration into the infrastructure as it currently exists. Fab-owning IDMs, for example, will be able to process TSVs in the front-end-of-line (FEOL), back-end-of-line (BEOL) or post-BEOL, as well as perform the thinning, aligning and bonding functions. They could also fabricate the TSVs in foundries and subsequently send the wafers to traditional outsourced semiconductor assembly and test suppliers (OSATs) for thinning, bonding and packaging.

However less convenient, fabless companies will also be able to have TSVs manufactured FEOL/BEOL at foundries, and thinning and bonding performed at an OSAT or potentially a foundry as well. If there is a need of post-BEOL TSV, the whole job can be processed at an OSAT.

Coming on board

Foundries are actively behind TSV technology. Last year, Chartered and Tezzaron jointly announced that Chartered would be scaling up Tezzaron's TSV technology.¹⁰ And Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) followed suit when T.W. Karta, senior director of back-end technology, announced "volume technology" and 140 μm pitch TSV technology in 2008, ramping to 60 μm pitch in 2009 and 17 μm in 2010.¹¹

Likewise, OSATs are preparing for production orders. In 2007, Amkor announced a collaborative agreement with IMEC to develop 3-D technology,¹² and their 3-D roadmap has targeted memory+memory and memory+logic stacking in the 2008–2010 timeframe.¹³ Amkor has also detailed its work on thinning and bonding for both copper and tungsten TSV.

2007 saw other OSATs coming on board: CTO Ho-Ming Tong announced ASE's work on 3-D integration with TSVs and anticipated production tied to the 45 nm node beginning in the 2008–2011 timeframe;¹⁰ and STATS ChipPAC announced the purchase of the Schott glass CMOS imaging chip packaging facility as well as the development of 3-D TSV technology at this site.¹⁰

For the most part, fabs will be inserting TSV on the front end, and the OSATs will be doing the rest of the process (thinning, bonding and backside processing).¹⁴

Beyond device fabrication, equipment and materials vendors are also a part of the growing 3-D infrastructure. In 2006, several equipment manufacturers, materials companies, and technology institutes joined together to form an international consortium, EMC-3D. The consortium's stated goal is to develop the 3-D market infrastructure by demonstrating a cost-effective, manufacturable, stackable TSV interconnection technology, with a third-year cost-of-ownership (CoO) goal of $200/wafer.¹⁵ The group includes Semitool, EV Group, Alcatel, XSil, RHEM, Enthone, Honeywell, AZ and Brewer Science. Another loosely affiliated equipment group started in 2008. Led by SUSS MicroTec, NEXX Systems and Surface Technology Systems (STS), this group is also focused on providing low-cost 3-D IC solutions.⁵

Signs of a ramp-up

Looking ahead to the next few years, 3-D IC technology appears poised to take off commercially. Keep an eye out for activity in FPGAs and design, and pay close attention to announcements from Samsung and Intel, for any one of these will surely signal a speedup of the overall adoption curve.

In design, although specific software is available from focused companies such as R3Logic, the major design houses like Cadence and Mentor Graphics have indicated that they are not yet convinced that the industry is "going this way."^13,16 An announcement by one of the EDA vendors will be another major indication that things are speeding up.

FPGAs have always had problems with interconnect delays. 3-D integration can improve performance by removing the programmable interconnect from the logic block layer and placing it on another tier in the stack, thus reducing the interconnect delay. Therefore, it is possible that FPGAs, with their simple repetitive structures, will adopt 3-D architectures faster than any other logic chip. Conceptually, memory could also be added as part of the 3-D tiers.

Samsung is a leader in DRAM, NAND, CIS and cell phone markets. The company is also a leader in 3-D TSV technology, as evidenced by prototypes it has shown of DRAM and NAND stacks. The company CEO announced at the 2006 IEEE International Electron Devices Meeting (IEDM), "The integration of memory, logic, sensors, processors and software will be based on die stacking 3-D technology." However, Samsung has not yet announced commercialization of 3-D technology, but has instead had an internal freeze on all commercialization information. Some have speculated that the chipmaker will sneak a 3-D stack into an internal cell phone product with no announcement until it is a success.¹⁷ Clearly, an official statement by Samsung would push the entire industry into an even faster commercialization pace.

Intel's Jerry Bautista commented at the 2007 3-D Architectures for Semiconductor Integration and Packaging conference that there were no remaining technical issues, and that Intel was ready to commercialize its 3-D integration technology as soon as the product groups decided which product to insert the technology into.¹⁸ Since the technology has been highlighted several times at the Intel designer's forum, and the company has published several technical papers on the overwhelming need to develop 3-D ICs for multicore processor technology, the world is waiting for Intel to pull the trigger on a product announcement.

Conclusion

All indications point toward massive adoption of 3-D IC technology as the short-term solution to the issues facing traditional device scaling. It appears that all phases of the infrastructure are in motion, integrating the technology and developing the necessary cost reduction measures to ensure 3-D's mainstream adoption. The next few years are likely to be very exciting for the microelectronics industry.

Author's note

For a much more comprehensive look at current 3-D IC technology, read the two-volume Handbook of 3D Integration, edited by Phil Garrou, Chris Bower and Peter Ramm, just published by Wiley-VCH.