The latest news and information on semiconductor lithography, including optical, EUV, e-beam, nanoimprint, maskless and other lithography techniques; exposure tools; resists; and masks/templates.
Litho Guru Optimistic About Nanoimprint Laura Peters, Editor-in-Chief - 04/30/2008
Ben Eynon, Director of Advanced Technology Development at Samsung (Seoul, South Korea) and Associate Director of Lithography at Sematech (Austin, Texas), discussed Samsung’s evaluation of nanoimprint lithography at the SEMI Strategic Business Conference (Napa Valley, Calif.). “The resolution is there for sure, it’s a matter of the defects and throughput,” he said. More
Maskless E-Beam Delivers 65 nm Prototypes Staff - 05/08/2008
Following successful 90 nm implementation, e-Shuttle Inc. is now delivering 65 nm CMOS logic ICs manufactured with electron-beam direct-write (EBDW) technology.
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Haze, Still Misunderstood, Costing Industry $1B a Year Aaron Hand, Executive Editor, Electronic Media - 05/07/2008
Arguably the single largest yield detractor in the semiconductor industry, costing the industry about a billion dollars every year, micro-contamination is still very little understood or acknowledged by semiconductor fabs. Industry experts discussed the issues and various solutions in a session yesterday on time-dependent haze at ESTECH 2008.
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Suss MicroTec to enhance nano imprinting with Philips Research litho technology By Ann Steffora Mutschler, Senior Editor - 04/29/2008
To improve printing resolution and repeatability in semiconductor manufacturing, Munich, Germany-based semiconductor test technology supplier Suss MicroTec has licensed Philips Research’s substrate conformal imprint lithography technology that will be added to an existing equipment platform for large-area imprint applications.
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TSMC Sketches 32 nm Rollout Plan for 2009 David Lammers, News Editor - 04/28/2008
Taiwan Semiconductor Manufacturing Co. Ltd. plans to begin 32 nm production in the third quarter of 2009, with foundry production of dual core 3G cell phone chipsets as one focus, said Jack Sun, TSMC’s vice president of R&D. TSMC will use a high-k/metal gate process for high-frequency microprocessor production, he said, while sticking with a poly/oxynitrides gate stack for the general purpose and low-power platforms.
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MAGIC Program Aims Maskless Lithography at 32 nm Aaron Hand, Executive Editor, Electronic Media - 04/24/2008
CEA-Leti (Grenoble, France) has officially launched a new research program on maskless electron-beam lithography, targeting maskless technology at the 32 nm half-pitch generation.
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Intel: 'EUV Facts Don't Add Up' for 22 nm in 2011 David Lammers, News Editor - 04/22/2008
Intel Senior Fellow Mark Bohr said EUV lithography will not be ready for volume production in 2011 when Intel intends to begin 22 nm microprocessor manufacturing. Intel’s lithography team has developed computational lithography techniques to extend ArF immersion lithography to 22 nm. “The facts don’t add up for EUV” in 2011, Bohr said.
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D2I Project Reduces Mask Inspection Time Kenji Tsuda, Asia Contributing Editor - 04/21/2008
Japan's national mask inspection project, Mask D2I, has figured out ways to significantly reduce mask inspection time. The mask review time is reduced by grouping detected defects and simplifying the threshold to distinguish between a defect and normal pattern.
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The Fine Print Aaron Hand, Executive Editor, Semiconductor International April 23, 2008 EUV at 16? Intel Still Pushing
When Intel speaks, people are generally interested. And when the überchipmaker s... More
Dan Herr is director of Nanomanufacturing Science Research at SRC. An important part of his research focuses on nanotechnology’s demands on metrology, and he discusses his work to determine where metrology technology’s gaps are, and how to fill them.
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Technical Articles
Etch's Role in Novel Logic Device Patterning Thorsten Lill, Applied Materials, Santa Clara, Calif., www.appliedmaterials.com; Steffen Schulze, Mentor Graphics, Wilsonville, Ore., www.mentor.com, 04/01/2008 The delay in the introduction of extreme ultraviolet (EUV) lithography has forced technologists to seek alternative patterning techniques using existing lithography tools for 32 and 22 nm devices. Splitting the tight pattern pitches, for example, of a line array into two separate masks with twice the regular space is one promising solution....
Novel CD-SEM Overlay Method Improves Dual Trench Patterning CDU Ilan Englard, Rich Piech, Liraz Gershtein, Ram Peltinov, Ofer Adan, Applied Materials Inc., Santa Clara, Calif., 02/01/2008
Using a trench-within-a-trench overlay mark and automated process control strategy, the CD uniformity issue associated with dual trench patterning can be kept within a production-worthy range....
Embedded OPC Extends Laser Mask Writers to 65/45 nm Anders Österberg, Micronic Laser Systems AB, Täby, Sweden; Steffen Schulze, Mentor Graphics Corp., Wilsonville, Ore., 02/01/2008
Embedded OPC can significantly enhance the CD linearity and proximity performance on photomasks by applying pre-patterning CD corrections to mask pattern data....
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Etch's Role in Novel Logic Device Patterning
