The latest news and information on semiconductor inspection, measurement and test, including metrology, microscopy, spectroscopy, spectrometry, CD measurement, defect detection/inspection, overlay and wafer inspection.
Memory Test Platform Handles Multiple Device Types Sally Cole Johnson, Contributing Editor - 11/25/2008
Verigy’s newest memory test family handles flash, DRAM and multichip packages (MCPs) — at the price of a flash tester. More
IEDM Panel: Processing Costs Headed Up David Lammers, News Editor - 12/17/2008
With more expensive tools and new process modules coming, IC manufacturers will struggle to maintain the cost-per-function reductions that have broadened the market for semiconductors. The likely introduction of 3-D interconnects, vertical transistors and EUV lithography all will add pressure on wafer processing costs, experts said at an evening panel discussion at the International Electron Devices Meeting going on in San Francisco this week.
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Multitest to Merge with Everett Charles Technologies Staff - 12/12/2008
Multitest Elektronische Systeme GmbH, which makes test handlers and test sockets, said it will merge with the Semiconductor Test Group of Everett Charles Technologies.
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Rudolph NSX Selected for Inspection of TSV Process Staff - 12/03/2008
Rudolph Technologies Inc. said that it has installed an NSX 115 Macro Inspection System at a major European fab. The NSX tool performs 2-D and 3-D metrology and inspection of defects during the same production cycle.
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NuFlare Orders Zeiss Mask Metrology Tool Staff - 12/03/2008
Carl Zeiss SMT disclosed one of the first orders for its next-generation mask metrology system from NuFlare Technology Inc. Developed by Zeiss with support from Sematech, the PROVE metrology system is considered a key building block for masks used in both 193 nm double patterning and EUV lithography.
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Applied Announces TSV Etcher, In-Fab Mask Inspection Capability David Lammers, News Editor - 12/01/2008
Applied Materials Inc. announced its Silvia deep silicon etcher for creation of the smooth sidewalls required for 3-D interconnects. Also, the company said it is offering a new version of its Aera2 mask inspection tool for use within a fab’s lithography cell, rather than at an external mask shop, needed for double patterning.
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Measuring Material, Dopant Loss From Post-Implant Wafer Cleans Nikki Edleman, IBM Microelectronics, Hopewell Junction, N.Y.; Yong-Siang Tan, Chartered Semiconductor Mfg. Ltd., Singapore; Tom Tillery, Stephen Savas, Andreas Kadavanich and Allan Wiesnoski, Mattson Technology, Fremont, Calif. - 11/01/2008
Maintaining the integrity of ultrashallow junctions (USJs) after exposure to an increasingnumber of high-dose implant resist cleaning steps is critical for logic device manufacturing at the 45 nm node and beyond. Use of SiGe in the PMOS regions adds an additional material challenge. A new short loop method provides accurate relative measurements of amorphized silicon or SiGe loss caused by different types of strip/clean processes.
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ISMI Outlines 450 mm Wafer, NGF Roadmaps David Lammers, News Editor - 10/27/2008
ISMI managers described progress at the 450 mm wafer Interoperability Test Bed, and described the Phase 2 roadmap at last week’s ISMI Symposium on Manufacturing Effectiveness. Also, the Next Generation Factory program at ISMI is continuing work on cycle time improvements for existing and greenfield 300 mm wafer fabs, including support for 12-wafer lots.
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The Measure of All Things Alexander E. Braun, Senior Editor, Semiconductor International August 26, 2008 He Saw It All First
A few days ago, while emptying an old filing cabinet my wife came across a thick ... More
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Technical Articles
Measuring Material, Dopant Loss From Post-Implant Wafer Cleans Nikki Edleman, IBM Microelectronics, Hopewell Junction, N.Y.; Yong-Siang Tan, Chartered Semiconductor Mfg. Ltd., Singapore; Tom Tillery, Stephen Savas, Andreas Kadavanich and Allan Wiesnoski, Mattson Technology, Fremont, Calif., 11/01/2008
Maintaining the integrity of ultrashallow junctions (USJs) after exposure to an increasingnumber of high-dose implant resist cleaning steps is critical for logic device manufacturing at the 45 nm node and beyond. Use of SiGe in the PMOS regions adds an additional material challenge. A new short loop method provides accurate relative measurements of amorphized silicon or SiGe loss caused by different types of strip/clean processes....
Inline Monitoring Detects CMOS Image Sensor Colorization Problems Jean-Charles Mattlin, STMicroelectronics, Rousset, France; Andreas Draeger, Vistec Semiconductor Systems, Weilburg, Germany, 10/01/2008
An optical non-destructive inspection method has been developed to detect colorization effects on CMOS image sensors. It can inspect 100% of the wafer surface, and is highly repeatable and reliable....
Concentration Sensors Curb Rising CoO Ron Chiarello, Jetalon Solutions Inc., Pleasant Hill, Calif., www.jetalon.com, Noritsugu Ishida, Swagelok Co., Solon, Ohio, 09/01/2008 In situ, real-time concentration monitoring will be vital to the industry's move to 65 nm CDs and below to address the need for increased yield and reduced waste....
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Measuring Material, Dopant Loss From Post-Implant Wafer Cleans
