The latest news and information on semiconductor clean processing, including wafer cleaning; photoresist stripping; cleanrooms; environment, safety and health; and contamination control.
Ulvac Enables Flexible Li-Ion Battery Kenji Tsuda, Asia Contributing Editor - 12/22/2008
Ulvac Inc. said it has developed a process flow for very thin lithium-ion cells, which may be combined with solar cells to create and store electricity in wearable electronics. The flexible battery features a solid-state electrolyte, which the company claims is safer than the conventional liquid electrolyte. The company adapted its semiconductor equipment and sputtering targets to the battery application. More
Ulvac Readies Resist Residue Removal Tool Staff - 12/05/2008
Ulvac Inc. demonstrated its recently released residue removal tool at SEMICON Japan. The Enviro Xceed 400 tool can remove >10 µm of resist residue per minute.
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Fab ESH: Prepare Better, Minimize Impact Sally Cole Johnson, Contributing Editor - 12/01/2008
The latest emphasis on green building and manufacturing, more efficient use of resources and preparing better for necessary changes makes for a safer, more environmentally friendly operation.
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FSI Enters Single-Wafer Clean Market Aaron Hand, Executive Editor, Electronic Media - 11/03/2008
FSI International (Chaska, Minn.) has made its single-wafer debut with its Orion cleaning system, which enables advanced wafer cleaning capabilities for such critical device structures as ultrashallow junctions, high-k/metal gates and metal capping layers. Innovative spray-bar and closed-chamber designs improve on competing single-wafer platforms, according to FSI’s Scott Becker.
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Measuring Material, Dopant Loss From Post-Implant Wafer Cleans Nikki Edleman, IBM Microelectronics, Hopewell Junction, N.Y.; Yong-Siang Tan, Chartered Semiconductor Mfg. Ltd., Singapore; Tom Tillery, Stephen Savas, Andreas Kadavanich and Allan Wiesnoski, Mattson Technology, Fremont, Calif. - 11/01/2008
Maintaining the integrity of ultrashallow junctions (USJs) after exposure to an increasingnumber of high-dose implant resist cleaning steps is critical for logic device manufacturing at the 45 nm node and beyond. Use of SiGe in the PMOS regions adds an additional material challenge. A new short loop method provides accurate relative measurements of amorphized silicon or SiGe loss caused by different types of strip/clean processes.
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Environmental Regulations Growing More Complex David Lammers, News Editor - 10/22/2008
Participants at an ISMI meeting on emerging environment, safety and health (ESH) regulations said the Stockholm Convention on Persistent Organic Pollutants is expected to vote on a ban of PFOS in May. The possible ban is part of an increasingly complex set of environmental regulations, with China taking an ever-dimmer view of potential contaminants.
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IMEC Views 3-D Stacking as System Design Laura Peters, Editor-in-Chief - 10/14/2008
IMEC managers said the research center has made significant progress creating test 3-D ICs, using die-to-die stacking. IMEC’s Eric Beyne said achieving coplanar and particle-free surfaces still presents processing challenges. He described the dual-damascene via processing as comparable to traditional front-end interconnect via processing, but with larger features.
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How Pump-Induced Particles Affect Low-k CMP Defectivity F.C. Chang, S. Tanawade and Rajiv Singh, Dept. of Materials Science and Engineering and Particle Engineering Research Center, University of Florida, Gainesville, Fla. - 09/01/2008 High shear flow generated by positive displacement pumps increases the distribution of oversized particles, leading to significantly increased wafer surface defectivity (scratches or roughness) during CMP, whereas less defectivity was found in slurries circulated by a magnetically levitated (maglev) centrifugal pump.More
Views on News David Lammers, News Editor, Semiconductor International May 6, 2008 The Other 450 mm Shoe
The three companies openly pushing for 450 mm wafers are working on a plan to subsidi... More
Views on News David Lammers, News Editor, Semiconductor International April 9, 2008 The Donut Mystery
John Halladay, a clean process manager at Spansion’s Fab 25, brought a good mys... More
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Technical Articles
Fab ESH: Prepare Better, Minimize Impact Sally Cole Johnson, Contributing Editor, 12/01/2008
The latest emphasis on green building and manufacturing, more efficient use of resources and preparing better for necessary changes makes for a safer, more environmentally friendly operation....
Measuring Material, Dopant Loss From Post-Implant Wafer Cleans Nikki Edleman, IBM Microelectronics, Hopewell Junction, N.Y.; Yong-Siang Tan, Chartered Semiconductor Mfg. Ltd., Singapore; Tom Tillery, Stephen Savas, Andreas Kadavanich and Allan Wiesnoski, Mattson Technology, Fremont, Calif., 11/01/2008
Maintaining the integrity of ultrashallow junctions (USJs) after exposure to an increasingnumber of high-dose implant resist cleaning steps is critical for logic device manufacturing at the 45 nm node and beyond. Use of SiGe in the PMOS regions adds an additional material challenge. A new short loop method provides accurate relative measurements of amorphized silicon or SiGe loss caused by different types of strip/clean processes....
How Pump-Induced Particles Affect Low-k CMP Defectivity F.C. Chang, S. Tanawade and Rajiv Singh, Dept. of Materials Science and Engineering and Particle Engineering Research Center, University of Florida, Gainesville, Fla., 09/01/2008 High shear flow generated by positive displacement pumps increases the distribution of oversized particles, leading to significantly increased wafer surface defectivity (scratches or roughness) during CMP, whereas less defectivity was found in slurries circulated by a magnetically levitated (maglev) centrifugal pump....
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Fab ESH: Prepare Better, Minimize Impact
