The latest news and information on semiconductor clean processing, including wafer cleaning; photoresist stripping; cleanrooms; environment, safety and health; and contamination control.
Haze, Still Misunderstood, Costing Industry $1B a Year Aaron Hand, Executive Editor, Electronic Media - 05/07/2008
Arguably the single largest yield detractor in the semiconductor industry, costing the industry about a billion dollars every year, micro-contamination is still very little understood or acknowledged by semiconductor fabs. Industry experts discussed the issues and various solutions in a session yesterday on time-dependent haze at ESTECH 2008. More
Applied Tackles Edge With Inflexion Polishing System David Lammers, News Editor, and Laura Peters, Editor-in-Chief - 05/07/2008
Applied Materials introduced the Inflexion edge polishing system that has an integrated wafer cleaning capability. The Inflexion tool uses abrasive tape to clean the wafer’s edge, an area that faces new contamination issues as immersion lithography pushes liquids to the edge of the wafer.
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SEZ Group Now Lam’s Spin Clean Division David Lammers, News Editor - 04/24/2008
Lam Research Corp. executives said they have created a Spin Clean Division to attack high-throughput, single-wafer cleaning opportunities. The spin clean tools acquired from the former SEZ Group will complement Lam’s linear clean tools, said Lam CEO Stephen Newberry.
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ITRS ESH Chapter Emphasizes Sustainable Development Aaron Hand, Executive Editor, Electronic Media - 04/16/2008
Sustainable development is the idea that manufacturing companies can satisfy their present requirements without compromising the needs of future generations. That’s a concept that figures prominently in the latest edition of the Environment, Safety and Health chapter of the International Technology Roadmap for Semiconductors.
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Clean Steps Struggle to Minimize Material Loss Aaron Hand, Executive Editor, Electronic Media - 04/10/2008
As noted throughout Sematech’s Surface Preparation and Cleaning Conference last week, cleaning processes are increasingly tasked to keep material losses to an absolute minimum. TI's Brian Kirkpatrick gave an invited presentation on the impact of material loss on advanced CMOS performance, pointing out that there are no easy solutions.
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New Materials Driving Wafer Cleaning Challenges David Lammers, News Editor - 04/03/2008
Wafer cleaning faces new challenges, as high-k dielectrics and metal gates are brought in at the 45 and 32 nm generations, said a panel of experts at the Sematech Surface Preparation and Cleaning Conference, held in Austin, Texas this week. Environmental safety and water and energy conservation are also adding to the broader surface preparation challenge, they agreed.
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Intel Tackles EUV Mask Cleans Aaron Hand, Executive Editor, Electronic Media - 04/02/2008
At Sematech’s Surface Preparation and Cleaning Conference in Austin, Texas, Intel’s Ted Liang detailed the results of a study designed to find solutions for adding zero particle contamination to EUV masks through the cleaning processes.
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iNEMI Launching Studies of Lead-Free Alloys Staff - 04/02/2008
The International Electronics Manufacturing Initiative (iNEMI) is forming projects related to lead-free alternatives used in packaging and board-level manufacturing, adoption of boundary scan technology, and solder paste deposition challenges.
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Views on News David Lammers, News Editor, Semiconductor International May 6, 2008 The Other 450 mm Shoe
The three companies openly pushing for 450 mm wafers are working on a plan to subsidi... More
Views on News David Lammers, News Editor, Semiconductor International April 9, 2008 The Donut Mystery
John Halladay, a clean process manager at Spansions Fab 25, brought a good mys... More
Dan Herr is director of Nanomanufacturing Science Research at SRC. An important part of his research focuses on nanotechnology’s demands on metrology, and he discusses his work to determine where metrology technology’s gaps are, and how to fill them.
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Technical Articles
Lower Thermal Budgets Affect Contamination Jerry Riddle, Chairman, Tiger Optics LLC, Warrington, Pa., www.tigeroptics.com, 01/01/2008 Tool builders and fab operators are constantly seeking ways to lower thermal budgets to speed throughput and use less resources, utilities and energy. However, what engineers have discovered is that with the lower-temperature process, contaminants that were not there at higher temperatures are increasingly present and remain in the process tools, pressure vessels, carriers and, in some cases, on the surface of the wafers....
Sustainable Chamber Cleaning Solutions: The Back End of the Front End Peter Lai and Paul Stockman, Linde Electronics, Murray Hill, N.J. Greg Shuttleworth, Linde Electronics, Thornton Cleveleys, UK, 01/01/2008
Sustainable and production-proven chamber cleaning solutions allow device manufacturers to deliver increased productivity and reduce environmental impact while "taking out the trash."...
Damage During Cleans Evaluated by AFM Peter Singer, Editor-in-Chief, 12/01/2007 An increasing problem with no known solution is the damage of small structures during wafer cleaning. The damage is seen as pattern collapse or simply as missing structures, blown off the surface of the wafer by the force of the clean. It's already a well-known result of aggressive megasonic cleans, but can also result from aerosol jet cleaning and newer laser-induced plasma shockwave cle......
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Lower Thermal Budgets Affect Contamination
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